Update README.md

README.md

@@ -31,7 +31,7 @@ This should run in the order of a few minutes.
 
 ## Scope
 
-Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.
+The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but yet to be fully tested. Support for compressed instructions may be added in the future as time permits.
 
 ## Known Issues
 

rvfi/insns/README.md

@@ -109,12 +109,19 @@ Below is a list of instructions currently supported by this port of the riscv-fo
     - `InsnSrlw`: SRLW instruction
     - `InsnSraw`: SRAW instruction
   - `InsnSd`: SD instruction
+  - `InsnRV64MRType`: RV64M R-Type Instruction
+    - `InsnMulw`: MULW instruction
+    - `InsnDivw`: DIVW instruction
+    - `InsnDivuw`: DIVUW instruction
+    - `InsnRemw`: REMW instruction
+    - `InsnRemuw`: REMUW instruction
 
 ### ISAs
 
 - `IsaRV32I`: RV32I Base ISA
 - `IsaRV32M`: RV32M Standard Extension
 - `IsaRV64I`: RV64I Base ISA
+- `IsaRV64M`: RV64M Standard Extension
 
 ## Core-specific parameters 
 

rvfi/insns/insn_addw.py

@@ -7,6 +7,7 @@ ADDW instruction
 class InsnAddw(InsnRV64IRType):
     def __init__(self, params):
         super().__init__(params, 0b0000000, 0b000)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_divuw.py

@@ -7,6 +7,7 @@ DIVUW instruction
 class InsnDivuw(InsnRV64MRType):
     def __init__(self, params):
         super().__init__(params, 0b101)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_divw.py

@@ -7,6 +7,7 @@ DIVW instruction
 class InsnDivw(InsnRV64MRType):
     def __init__(self, params):
         super().__init__(params, 0b100)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_mulw.py

@@ -7,6 +7,7 @@ MULW instruction
 class InsnMulw(InsnRV64MRType):
     def __init__(self, params):
         super().__init__(params, 0b000)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_remuw.py

@@ -7,6 +7,7 @@ REMUW instruction
 class InsnRemuw(InsnRV64MRType):
     def __init__(self, params):
         super().__init__(params, 0b111)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_remw.py

@@ -7,6 +7,7 @@ REMW instruction
 class InsnRemw(InsnRV64MRType):
     def __init__(self, params):
         super().__init__(params, 0b110)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_rv64i_i_type_load.py

@@ -10,6 +10,7 @@ class InsnRV64IITypeLoad(InsnRV64IIType):
         self.mask_shift = mask_shift
         self.funct3 = funct3
         self.is_signed = is_signed
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_rv64i_i_type_shift.py

@@ -9,6 +9,7 @@ class InsnRV64IITypeShift(InsnRV64IIType):
         super().__init__(params)
         self.funct6 = funct6
         self.funct3 = funct3
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_rv64i_r_type.py

@@ -9,6 +9,7 @@ class InsnRV64IRType(Insn):
         super().__init__(params)
         self.funct7 = funct7
         self.funct3 = funct3
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_rv64m_r_type.py

@@ -8,6 +8,7 @@ class InsnRV64MRType(Insn):
     def __init__(self, params, funct3):
         super().__init__(params)
         self.funct3 = funct3
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_slliw.py

@@ -7,6 +7,7 @@ SLLIW instruction
 class InsnSlliw(InsnRV64IITypeShift):
     def __init__(self, params):
         super().__init__(params, 0b000000, 0b001)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_sllw.py

@@ -7,6 +7,7 @@ SLLW instruction
 class InsnSllw(InsnRV64IRType):
     def __init__(self, params):
         super().__init__(params, 0b0000000, 0b001)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_sraiw.py

@@ -7,6 +7,7 @@ SRAIW instruction
 class InsnSraiw(InsnRV64IITypeShift):
     def __init__(self, params):
         super().__init__(params, 0b010000, 0b101)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_sraw.py

@@ -7,6 +7,7 @@ SRAW instruction
 class InsnSraw(InsnRV64IRType):
     def __init__(self, params):
         super().__init__(params, 0b0100000, 0b101)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_srliw.py

@@ -7,6 +7,7 @@ SRLIW instruction
 class InsnSrliw(InsnRV64IITypeShift):
     def __init__(self, params):
         super().__init__(params, 0b000000, 0b101)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_srlw.py

@@ -7,6 +7,7 @@ SRLW instruction
 class InsnSrlw(InsnRV64IRType):
     def __init__(self, params):
         super().__init__(params, 0b0000000, 0b101)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)
 

rvfi/insns/insn_subw.py

@@ -7,6 +7,7 @@ SUBW instruction
 class InsnSubw(InsnRV64IRType):
     def __init__(self, params):
         super().__init__(params, 0b0100000, 0b000)
+
     def elaborate(self, platform):
         m = super().elaborate(platform)