M-Labs/riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Update README.md

Browse Source
This commit is contained in:
Donald Sebastian Leung 2020-08-27 12:54:28 +08:00
parent 0954ee7fa9
commit dae95900b6
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
rvfi/insns/README.md
View File

@ -97,6 +97,7 @@ Below is a list of instructions currently supported by this port of the riscv-fo
- `InsnRV64IITypeLoad`: RV64I I-Type Instruction (Load Variation)
- `InsnLwu`: LWU instruction
- `InsnLd`: LD instruction
- `InsnSd`: SD instruction
### ISAs