Add SRLIW instruction
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@ -1,5 +1,9 @@
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from .insn_rv64i_i_type_shift import *
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"""
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SLLIW instruction
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"""
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class InsnSlliw(InsnRV64IITypeShift):
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def __init__(self, params):
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super().__init__(params, 0b000000, 0b001)
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@ -0,0 +1,17 @@
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from .insn_rv64i_i_type_shift import *
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"""
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SRLIW instruction
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"""
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class InsnSrliw(InsnRV64IITypeShift):
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def __init__(self, params):
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super().__init__(params, 0b000000, 0b101)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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result = Signal(32)
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m.d.comb += result.eq(self.rvfi_rs1_rdata[:32] >> self.insn_shamt)
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m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
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return m
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