riscv-formal-nmigen/rvfi
Donald Sebastian Leung a58842ea94 Add MULHSU instruction 2020-08-26 16:39:17 +08:00
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checks Replace individual instruction checks with ISA check 2020-08-21 15:14:42 +08:00
cores Add prototype for instruction/data bus implementation 2020-08-25 12:41:30 +08:00
insns Add MULHSU instruction 2020-08-26 16:39:17 +08:00
__init__.py Modularize codebase 2020-08-17 11:50:53 +08:00