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riscv-formal-nmigen
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Add SD instruction

master
Donald Sebastian Leung 2020-08-27 12:53:07 +08:00
parent 472e0a70f8
commit 0954ee7fa9
1 changed files with 42 additions and 0 deletions
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rvfi/insns/insn_sd.py Normal file
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from .insn import *
"""
SD instruction
"""
class InsnSd(Insn):
def elaborate(self, platform):
m = super().elaborate(platform)
m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
if self.params.csr_misa:
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
m.d.comb += self.spec_csr_misa_rmask.eq(0)
else:
m.d.comb += self.misa_ok.eq(1)
if self.params.aligned_mem:
addr = Signal(self.params.xlen)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0100011))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_mem_addr.eq(addr & ~(self.params.xlen // 8 - 1))
m.d.comb += self.spec_mem_wmask.eq(((1 << 8) - 1) << (addr - self.spec_mem_addr))
m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (addr - self.spec_mem_addr)))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(((addr & (8 - 1)) != 0) | ~self.misa_ok)
else:
addr = Signal(self.params.xlen)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0100011))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_mem_addr.eq(addr)
m.d.comb += self.spec_mem_wmask.eq((1 << 8) - 1)
m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(~self.misa_ok)
return m