Add RV64I I-Type Instruction

This commit is contained in:
Donald Sebastian Leung 2020-08-27 11:46:04 +08:00
parent fe835e272d
commit 0af1f20423

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@ -0,0 +1,19 @@
from .insn import *
"""
RV64I I-Type Instruction
"""
class InsnRV64IIType(Insn):
def elaborate(self, platform):
m = super().elaborate(platform)
m.d.comb += self.insn_imm.eq(Value.as_signed(sefl.rvfi_insn[20:32]))
if self.params.csr_misa:
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
m.d.comb += self.spec_csr_misa_rmask.eq(0)
else:
m.d.comb += self.misa_ok.eq(1)
return m