Donald Sebastian Leung 94c19ed7f7 Add SRLIW instruction		2020-08-27 13:42:38 +08:00
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checks	Replace individual instruction checks with ISA check	2020-08-21 15:14:42 +08:00
cores	Replace RV32I with RV32M for Minerva verification tasks	2020-08-27 10:48:35 +08:00
insns	Add SRLIW instruction	2020-08-27 13:42:38 +08:00
__init__.py	Modularize codebase	2020-08-17 11:50:53 +08:00