Donald Sebastian Leung d188b9cdac Add SRLW instruction		2020-08-27 15:56:36 +08:00
..
checks	Replace individual instruction checks with ISA check	2020-08-21 15:14:42 +08:00
cores	Replace RV32I with RV32M for Minerva verification tasks	2020-08-27 10:48:35 +08:00
insns	Add SRLW instruction	2020-08-27 15:56:36 +08:00
__init__.py	Modularize codebase	2020-08-17 11:50:53 +08:00