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a9f1431959
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Record failing instructions in individual instruction checks
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2020-09-07 15:43:39 +08:00 |
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d84852e368
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Replace unconditional pass and OOM issue with assertion failure
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2020-09-07 12:32:14 +08:00 |
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d25785c4b4
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Update README.md to reflect support for 64-bit ISAs
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2020-08-28 12:33:14 +08:00 |
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b3acff2bf3
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Update README.md
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2020-08-28 12:30:39 +08:00 |
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e117fad73d
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Add RV64M Standard Extension
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2020-08-28 12:20:56 +08:00 |
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9b4644e905
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Add REMUW instruction
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2020-08-28 12:04:51 +08:00 |
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64964655ff
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Add REMW instruction
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2020-08-28 12:01:00 +08:00 |
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f1a5da1a34
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Add DIVUW instruction
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2020-08-28 11:55:11 +08:00 |
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b9f96a8ad0
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Add DIVW instruction
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2020-08-28 11:52:09 +08:00 |
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1eab79538a
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Add MULW instruction
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2020-08-28 11:45:45 +08:00 |
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8fa2a33ecf
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Add RV64M R-Type Instruction
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2020-08-28 11:37:54 +08:00 |
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5d17b917b4
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Update README.md
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2020-08-27 16:25:54 +08:00 |
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fe5e73b6cb
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Add RV64I Base ISA
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2020-08-27 16:21:53 +08:00 |
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e7066b8c89
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Add SRAW instruction
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2020-08-27 16:04:00 +08:00 |
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d188b9cdac
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Add SRLW instruction
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2020-08-27 15:56:36 +08:00 |
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b60b590fe1
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Add SLLW instruction
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2020-08-27 15:54:01 +08:00 |
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956be6570d
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Add SUBW instruction
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2020-08-27 15:50:30 +08:00 |
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2055f5159b
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Add ADDW instruction
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2020-08-27 15:48:11 +08:00 |
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6e4ecdcee0
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Add RV64I R-Type Instruction
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2020-08-27 15:39:09 +08:00 |
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cf295596ef
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Update README.md
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2020-08-27 13:53:49 +08:00 |
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ade3d46b5b
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Add SRAIW instruction
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2020-08-27 13:52:20 +08:00 |
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94c19ed7f7
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Add SRLIW instruction
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2020-08-27 13:42:38 +08:00 |
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d837f6f8f6
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Add SLLIW instruction
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2020-08-27 13:39:11 +08:00 |
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2790cb1f4c
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Add RV64I I-Type Instruction (Shift Variation)
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2020-08-27 13:28:29 +08:00 |
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a15e57e12e
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Update README.md
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2020-08-27 13:12:23 +08:00 |
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3a332c5c1d
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Add ADDIW instruction
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2020-08-27 13:11:23 +08:00 |
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dae95900b6
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Update README.md
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2020-08-27 12:54:28 +08:00 |
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0954ee7fa9
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Add SD instruction
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2020-08-27 12:53:07 +08:00 |
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472e0a70f8
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Update README.md
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2020-08-27 12:30:57 +08:00 |
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94da2671dc
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Add LD instruction
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2020-08-27 12:28:19 +08:00 |
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bd76a47a52
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Add LWU instruction
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2020-08-27 12:25:19 +08:00 |
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92e34efe0d
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Add RV64I I-Type Instruction (Load Variation)
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2020-08-27 12:20:17 +08:00 |
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0af1f20423
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Add RV64I I-Type Instruction
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2020-08-27 11:46:04 +08:00 |
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fe835e272d
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Replace RV32I with RV32M for Minerva verification tasks
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2020-08-27 10:48:35 +08:00 |
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1ea25a4886
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Add RV32M Standard Extension
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2020-08-27 10:32:49 +08:00 |
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3f3ec597a1
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Update README.md
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2020-08-26 17:21:27 +08:00 |
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46e6ca3f70
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Add REMU instruction
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2020-08-26 17:15:27 +08:00 |
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fb91df7bb8
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Add REM instruction
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2020-08-26 17:11:03 +08:00 |
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33ace9147a
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Add DIVU instruction
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2020-08-26 17:03:49 +08:00 |
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0708f6b962
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Add DIV instruction
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2020-08-26 16:58:50 +08:00 |
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b74a0cf699
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Add MULHU instruction
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2020-08-26 16:43:21 +08:00 |
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a58842ea94
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Add MULHSU instruction
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2020-08-26 16:39:17 +08:00 |
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15580a74c6
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Add MULH instruction
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2020-08-26 16:30:54 +08:00 |
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585965ee0a
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Add MUL instruction
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2020-08-26 15:57:32 +08:00 |
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dd17606902
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Add RV32M R-Type Instruction
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2020-08-26 15:48:55 +08:00 |
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ca9e9c9ca6
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Add prototype for instruction/data bus implementation
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2020-08-25 12:41:30 +08:00 |
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ac7991ae86
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Merge instruction and data bus abstractions
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2020-08-25 10:12:02 +08:00 |
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ca135d024f
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Wire instruction and data buses (WIP) to Minerva core
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2020-08-24 14:46:52 +08:00 |
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2a4f6dd07e
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Wire interrupt signals to Minerva for verification
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2020-08-24 13:28:33 +08:00 |
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ee80bff3db
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Merge riscv_formal_parameters.py into verify.py
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2020-08-24 10:20:30 +08:00 |
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