Mikołaj Sowiński
3c7ab498d1
Added DDS selection for Kasli tester variant
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Signed-off-by: Mikołaj Sowiński <msowinski@technosystem.com.pl>
2022-09-02 17:14:23 +08:00
cc78078
3535d0f1ae
kasli: relocate the SatelliteBase Error LED code ( #1955 )
2022-08-12 12:41:50 +08:00
cc78078
185c91f522
kasli: add Error LED to MasterBase and SatelliteBase
2022-08-11 15:06:58 +08:00
Etienne Wodey
9f830b86c0
kasli: add SED lanes count option to HW description JSON file ( #1745 )
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Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-12-03 17:05:35 +08:00
Peter Drmota
20e079a381
AD9910 driver feature extension and SUServo IIR readability ( #1500 )
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* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync
* SUServo: Wrap CPLD and DDS devices in a list
* SUServo: Refactor [nfc]
Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
2021-11-15 12:09:16 +08:00
occheung
cb247f235f
gateware: pass adr_w/data_w to submodules
2021-11-08 16:59:08 +08:00
occheung
d84ad0095b
comm_cpu: select 64b bus if not kasli v1.x
2021-11-08 16:59:08 +08:00
Spaqin
1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path ( #1760 )
2021-10-07 08:19:38 +08:00
occheung
1b516b16e2
targets: default to vexriscv cpu
2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
7dfb4af682
kasli2: work around vivado clock constraint problem
2020-10-08 16:31:39 +08:00
Sebastien Bourdeauducq
96a5df0dc6
kasli2: add false path constraint for wrpll helper clock
2020-10-08 16:19:44 +08:00
Sebastien Bourdeauducq
29c940f4e3
kasli2: forward sma_clkin to si5324
2020-09-17 16:53:43 +08:00
Astro
002a71dd8d
build_soc: rename identifier_str to gateware_identifier_str
2020-09-02 00:00:57 +08:00
Astro
45ae6202c0
build_soc: add identifier_str override option
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Signed-off-by: Stephan Maka <stephan@spaceboyz.net>
2020-08-31 11:48:58 +08:00
Sebastien Bourdeauducq
4e9a529e5a
kasli: integrate WRPLL
2020-05-07 21:34:02 +08:00
Sebastien Bourdeauducq
60e5f1c18e
kasli: DRTIO support for Kasli 2
2020-05-07 20:09:43 +08:00
Sebastien Bourdeauducq
1f2182d4c7
kasli: default to hardware v2
2020-05-07 19:15:03 +08:00
Sebastien Bourdeauducq
b83afedf43
kasli: light up ERROR LED on panic
2020-05-07 19:06:10 +08:00
Sebastien Bourdeauducq
7e400a78f4
kasli: compile tester for hw 2.0 by default
2020-04-28 16:07:56 +08:00
Sebastien Bourdeauducq
d19f28fa84
kasli: v2 clocking WIP, remove SFP LEDs from RTIO
2020-04-23 23:02:18 +08:00
Sebastien Bourdeauducq
42af76326f
kasli: enlarge integrated CPU SRAM for DRTIO masters
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Required by the bootloader netboot support.
2019-11-01 10:15:13 +08:00
Sebastien Bourdeauducq
462cf5967e
bootloader: add netboot support
2019-10-30 21:23:42 +08:00
Sebastien Bourdeauducq
314d9b5d06
kasli: default to 125MHz frequency for DRTIO
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This is the consistent and most common option. Sayma will also eventually move to it.
2019-10-08 12:59:52 +08:00
Sebastien Bourdeauducq
21021beb08
kasli: remove opticlock (moved to kasli_generic)
2019-09-09 15:03:10 +08:00
Robert Jördens
ead9a42842
kasli: remove VLBAIMaster, VLBAISatellite variants
2019-05-08 15:58:25 +00:00
Robert Jördens
0c9b810501
kasli: remove PTB/PTB2/LUH/HUB variants
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see sinara-systems and nix-scripts repos
2019-05-08 15:51:18 +00:00
David Nadlinger
4d215cf541
firmware: Add Si5324 config for 125 MHz ext ref
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PLL divider settings as suggested by DSPLLsim 5.1.
2019-04-15 22:22:19 +01:00
Chris Ballance
4499ef1748
kasli: only add moninj core if there are probes to monitor
2019-03-24 14:09:52 +08:00
Sebastien Bourdeauducq
de3992bbdd
kasli: remove HUST variants (supported by kasli_generic)
2019-02-23 15:44:17 +08:00
Sebastien Bourdeauducq
1c35c051a5
kasli: remove variants supported by generic builder
2019-02-22 23:08:49 +08:00
Sebastien Bourdeauducq
ff4e4f15ed
kasli: expose base SoC classes
2019-02-12 18:33:27 +08:00
Sebastien Bourdeauducq
1cfd26dc2e
kasli: add UNSW variant
2019-02-08 17:51:51 +08:00
Sebastien Bourdeauducq
b56c7cec1e
kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target
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Urukul sync is not reliable at 125/1000
2019-02-05 11:24:45 +08:00
Sebastien Bourdeauducq
07b5b0d36d
kasli: adapt Master target to new hardware
2019-01-24 18:27:15 +08:00
Sebastien Bourdeauducq
154269b77a
kasli: fix HUST satellite Urukul
2019-01-23 17:59:43 +08:00
Sebastien Bourdeauducq
d7e6f104d2
kasli: add HUST variants
2019-01-23 14:11:51 +08:00
Sebastien Bourdeauducq
81f2b2c864
kasli: remove unpopulated Tester EEMs
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* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester)
* shortens compilation times
2019-01-23 12:14:44 +08:00
Sebastien Bourdeauducq
9ee5fea88d
kasli: support optional SATA port for DRTIO
2019-01-22 18:06:48 +08:00
Sebastien Bourdeauducq
bff8c8cb05
kasli: add Berkeley variant
2019-01-21 17:44:17 +08:00
David Nadlinger
1c71ae636a
examples: Add edge counters to kasli_tester variant
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This enables test_edge_counter on the CI system.
2019-01-15 10:55:07 +00:00
Sebastien Bourdeauducq
77126ce5b3
kasli: use hwrev 1.1 by default for DRTIO examples
2019-01-02 23:04:20 +08:00
Sebastien Bourdeauducq
ab9ca0ee0a
kasli: use 150MHz for DRTIO by default (Sayma compatibility)
2019-01-02 23:03:57 +08:00
Sebastien Bourdeauducq
cc58318500
siphaser: autocalibrate skew using RX synchronizer
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* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
2019-01-02 22:29:27 +08:00
Sebastien Bourdeauducq
53e79f553f
Merge branch 'master' into new
2018-11-19 11:54:50 +08:00
Sebastien Bourdeauducq
78d4b3a7da
gateware/targets: expose variant lists
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This allows writing scripts that build all variants.
2018-11-17 22:10:20 +08:00
Sebastien Bourdeauducq
c990b5e4f1
Merge remote-tracking branch 'origin/master' into new
2018-11-08 20:21:56 +08:00
Sebastien Bourdeauducq
ad0254c17b
Merge branch 'switching125' into new
2018-11-07 22:03:18 +08:00
Sebastien Bourdeauducq
efd735a6ab
Revert "drtio: monitor RTIOClockMultiplier PLL ( #1155 )"
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This reverts commit 469a66db61
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2018-11-07 22:01:03 +08:00
Robert Jördens
ba4bf6e59b
kasli: don't pass rtio pll feedback through bufg
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UG472: "The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it
never passes through a block powered by this supply."
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:58:55 +00:00
Robert Jördens
b6e4961b0f
kasli: lower RTIO clock jitter
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* high bandwidth since the si5324 is good
* no low power ibufgds
* drop bufg between ibufgds and pll
* increase pll vco frequency to 1.5 GHz
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:43:19 +00:00