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168 Commits

Author SHA1 Message Date
Robert Jördens e17e458c58 ptb2: add sync to urukul0 for ad9910 usage 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 10:06:51 +00:00
Robert Jördens 31f68ddf6c Merge branch 'urukul-sync' 
* urukul-sync: (29 commits)
  urukul: flake8 [nfc]
  ad9910: flake8 [nfc]
  urukul/ad9910 test: remove unused import
  test_urukul: relax speed
  urukul,ad9910: print speed metrics
  kasli: add PTB2 (external clock and SYNC)
  kasli: add sync to LUH, HUB, Opticlock
  kasli_tester: urukul0 mmcx clock defunct
  test_ad9910: relax ifc mode read
  tests: add Urukul-AD9910 HITL unittests including SYNC
  ad9910: add init bit explanation
  test: add Urukul CPLD HITL tests
  ad9910: fiducial timestamp for tracking phase mode
  ad9910: add phase modes
  ad9910: fix pll timeout loop
  tester: add urukul sync
  ptb: back out urukul-sync
  ad9910: add IO_UPDATE alignment and tuning
  urukul: set up sync_in generator
  ad9910: add io_update alignment measurement
  ...

close #1143
 2018-11-05 19:54:30 +01:00
Robert Jördens 32d538f72b kasli: add PTB2 (external clock and SYNC) 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:16 +01:00
Robert Jördens d8a5951a13 kasli: add sync to LUH, HUB, Opticlock 
for #1143, also add missing LUH device db

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:14 +01:00
Robert Jördens 4269d5ad5c tester: add urukul sync 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:52 +01:00
Robert Jördens 60d3bc63a7 ptb: back out urukul-sync 
... for backwards compatibility.

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:50 +01:00
Robert Jördens 0433e8f4fe urukul: add sync_in generator 
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:30 +01:00
Sebastien Bourdeauducq bc4a8157c0 kasli: add tsinghua2 2018-11-01 18:26:37 +08:00
Sebastien Bourdeauducq 6357a50d33 kasli: update nudt variant 2018-10-15 18:04:57 +08:00
Sebastien Bourdeauducq 469a66db61 drtio: monitor RTIOClockMultiplier PLL (#1155) 
Debugging by Tom Harty
 2018-10-08 14:50:02 +02:00
Sebastien Bourdeauducq 86fe6b0594 kasli: add NUDT variant 2018-10-04 23:20:09 +08:00
Sebastien Bourdeauducq a89bd6b684 kasli: swap Urukul EEMs for Tester 
Updated to Urukul 1.3.
 2018-10-04 23:19:31 +08:00
Sebastien Bourdeauducq 9f96b6bcda kasli: use 125MHz DRTIO freq for testing 2018-10-04 10:41:01 +08:00
Sebastien Bourdeauducq 969a305c5a Merge branch 'master' into switching125 2018-10-04 10:08:42 +08:00
Robert Jördens d0ee2c2955 opticlock: external 100 MHz 2018-09-28 19:05:18 +02:00
Sebastien Bourdeauducq 3b3fddb5a4 kasli: add mitll2 2018-09-27 23:21:52 +08:00
Sebastien Bourdeauducq b92350b0f6 drtio: monitor RTIOClockMultiplier PLL (#1155) 
Debugging by Tom Harty
 2018-09-26 10:52:08 +08:00
Sebastien Bourdeauducq 212892d92f style 2018-09-26 10:13:33 +08:00
Sebastien Bourdeauducq cd61ee858c kasli: fix satellite TSC instantiation 2018-09-15 14:06:54 +08:00
Sebastien Bourdeauducq 420e1cb1d0 cri: fix firmware routing table access 2018-09-12 18:08:16 +08:00
Sebastien Bourdeauducq 7ec45efdcf kasli: add missing cri_con to Satellite 2018-09-10 20:16:09 +08:00
Sebastien Bourdeauducq 7ae44f3417 firmware: add routing table (WIP) 2018-09-09 21:49:28 +08:00
Sebastien Bourdeauducq 496d1b08fd kasli: enable routing in Master 2018-09-09 21:48:12 +08:00
Sebastien Bourdeauducq ec302747e0 kasli: add DRTIO repeaters 2018-09-09 16:27:39 +08:00
Sebastien Bourdeauducq 87e0384e97 drtio: separate aux controller 
This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
 2018-09-05 17:56:58 +08:00
Sebastien Bourdeauducq 3d531cc923 kasli: adapt to TSC and DRTIOSatellite changes 2018-09-05 12:06:47 +08:00
Robert Jördens 47eb37e212 VLBAI{Master,Slave}: align rtio channels with PTB 2018-09-04 10:39:45 +00:00
Robert Jördens e7dba34475 kasli/tester: fill all 12 EEM 2018-08-29 18:09:09 +00:00
Robert Jördens fbf05db5ab kasli: add VLBAI Master and Satellite 2018-08-29 17:53:48 +00:00
Robert Jördens 9584c30a1f kasli: DRTIO Base: flexible rtio_clk_freq 2018-08-29 17:53:48 +00:00
Sebastien Bourdeauducq 9b6ea47b7a kasli: use SFP LEDs to show DRTIO link status. Closes #1073 2018-08-19 13:04:41 +08:00
Sebastien Bourdeauducq 9ce6233926 kasli: fix SYSU TTL directions 2018-08-07 19:29:28 +08:00
Sebastien Bourdeauducq 65f198bdee kasli: use tester EEMs for DRTIO, add Urukul-Sayma sync example 2018-08-06 16:53:13 +08:00
Sebastien Bourdeauducq 3638a966e1 kasli: add false path between RTIO and CL clocks 2018-07-21 13:26:13 +08:00
Sebastien Bourdeauducq b27fa8964b add variant in identifier string 
Also add without-sawg suffixes on Sayma.

Closes #1060
Closes #1059
 2018-07-15 17:21:17 +08:00
Sebastien Bourdeauducq 509562ddbf kasli: add WIPM target 2018-07-06 15:41:28 +08:00
Sebastien Bourdeauducq cae92f9b44 kasli: add Tsinghua variant 2018-06-06 19:03:45 +08:00
Robert Jördens f50aef1a22 suservo: extract boilerplate 
closes #1041
 2018-06-01 15:37:07 +00:00
Paweł 44c7a028cb Added second argument to DIO.add_STD in master and satellite variant of kasli (now builds properly) 2018-05-30 22:49:40 +08:00
Sebastien Bourdeauducq ad099edf63 kasli: integrate grabber 2018-05-28 22:43:40 +08:00
Robert Jördens b20a8c86b0 kasli: don't bother with grabber ttls for now 
not used on target cameras
 2018-05-28 07:31:00 +02:00
Sebastien Bourdeauducq 80c69da17e eem: add Grabber IOs and CC 2018-05-28 11:16:23 +08:00
Robert Jördens b09d07905c kasli: add LUH/PTB/HUB variants 
and refactor/simplify variant selection
 2018-05-27 18:33:27 +00:00
Sebastien Bourdeauducq 19efd8b13e kasli: refactor EEM code 2018-05-24 18:41:54 +08:00
Sebastien Bourdeauducq 4e5fe672e7 kasli: add tester target 2018-05-21 17:43:39 +08:00
Sebastien Bourdeauducq 72aef5799e kasli/ustc: use TTLOut 2018-05-18 22:55:28 +08:00
Sebastien Bourdeauducq b10d3ee4b4 make RTIO clock switch optional and simplify 
Kasli no longer has an internal RTIO clock.
Switching clocks dynamically is no longer supported.
 2018-05-18 17:41:34 +08:00
Sebastien Bourdeauducq 8a988d0feb kasli: remove leftover debug print 2018-05-18 17:25:23 +08:00
Sebastien Bourdeauducq 37bd0c2566 kasli: add USTC target 2018-05-18 16:15:07 +08:00
Robert Jördens 27f975e7bb kasli: eem DifferentialInputs need DIFF_TERM 
cleanup some formatting on the way
 2018-05-14 12:26:49 +00:00
Sebastien Bourdeauducq 8c1390e557 kasli: use 62.5MHz clock for siphaser reference (#999) 2018-05-12 22:58:03 +08:00
Robert Jördens 7d4a103a43 opticlock, suservo: set default kasli hw_rev 2018-05-07 09:07:18 +02:00
Robert Jördens 5a683ddd1f Revert "kasli: force hw_rev for the different targets" 
This reverts commit 17d7d7856a.

Would require filtering it in misoc or better
removing the argparse option.
 2018-04-28 23:24:41 +02:00
Robert Jördens 17d7d7856a kasli: force hw_rev for the different targets 2018-04-28 21:30:29 +02:00
Robert Jördens 307cd07b9d suservo: lots of gateware/ runtime changes 
tested/validated:

* servo enable/disable
* dds interface, timing, io_update, mask_nu
* channel control (en_out, en_iir, profile)
* profile configuration (coefficients, delays, offsets, channel)
* adc timings and waveforms measured
* asf state readback
* adc readback

individual changes below:

suservo: correct rtio readback

suservo: example, device_db [wip]

suservo: change rtio channel layout

suservo: mem ports in rio domain

suservo: sck clocked from rio_phy

suservo: cleanup, straighten out timing

suservo: dds cs polarity

suservo: simplify pipeline

suservo: drop unused eem names

suservo: decouple adc SR from IIR

suservo: expand coredevice layer

suservo: start the correct stage

suservo: actually load ctrl

suservo: refactor/tweak adc timing

suservo: implement cpld and dds init
 2018-04-27 13:50:26 +02:00
Robert Jördens f9b2c32739 suservo: add pgia spi channel 2018-04-25 17:14:25 +00:00
Robert Jördens 37c186a0fc suservo: refactor, constrain 
* remove DiffMixin, move pad layout handling to pads
* add input delay constraints, IDELAYs
 2018-04-25 13:44:52 +00:00
Robert Jördens d0258b9b2d suservo: set input delays 2018-04-24 15:30:25 +00:00
Robert Jördens 3942c2d274 suservo: fix clkout cd drive 2018-04-24 10:18:32 +00:00
Robert Jördens f74998a5e0 suservo: move arch logic to top, fix tests 2018-04-23 21:11:26 +00:00
Robert Jördens 929ed4471b kasli/SUServo: use suservo, implement urukul_qspi 
m-labs/artiq#788
 2018-04-23 18:30:18 +00:00
Sebastien Bourdeauducq eac447278f kasli: add MITLL variant 2018-04-17 19:00:11 +08:00
Sebastien Bourdeauducq 756e120c27 kasli/sysu: add comments 2018-04-17 18:46:55 +08:00
Sebastien Bourdeauducq 493d2a653f siphaser: add false path between sys_clk and mmcm_freerun_output 2018-03-29 10:55:41 +08:00
Sebastien Bourdeauducq 4229c045f4 kasli: fix DRTIO master clock constraint 2018-03-29 10:20:31 +08:00
Sebastien Bourdeauducq 605292535c kasli: ignore OSERDESE2->ISERDESE2 timing path on DRTIO targets as well 2018-03-29 10:12:02 +08:00
Robert Jördens 770b0a7b79 novogorny: conv -> cnv 
* parity with sampler
* also add novogorny device to opticlock
 2018-03-21 18:38:42 +00:00
Robert Jördens 1afce8c613 kasli: simplify single eem pin formatting 2018-03-21 13:08:42 +01:00
Robert Jördens d48b8f3086 kasli: fix sampler sdr/cnv pins 2018-03-21 09:28:00 +00:00
Robert Jördens 1fb5907362 kasli: add SUServo variant (Sampler-Urukul Servo) 2018-03-21 08:53:26 +00:00
Robert Jördens f74d5772f4 sampler: add wide eem definition 2018-03-21 08:53:26 +00:00
Thomas Harty 37d431039d Fix typos. 
Reduce ififo depth to 4 for Zotino.
 2018-03-19 09:42:18 +00:00
Thomas Harty c4fa44bc62 Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock. 2018-03-18 00:25:43 +00:00
Sebastien Bourdeauducq fc3d97f1f7 drtio: remove spurious multichannel transceiver clock constraints 
They used to cause (otherwise harmless) Vivado critical warnings.
 2018-03-09 22:46:27 +08:00
Sebastien Bourdeauducq caf7b14b55 kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code 2018-03-09 22:36:16 +08:00
Robert Jördens 82831a85b6 kasli/opticlock: add eem6 phys 2018-03-07 21:32:59 +01:00
Sebastien Bourdeauducq 916197c4d7 siphaser: cleanup 2018-03-07 11:15:44 +08:00
Sebastien Bourdeauducq c34d00cbc9 drtio: implement Si5324 phaser gateware and partial firmware support 2018-03-07 10:57:30 +08:00
Robert Jördens 62af7fe2ac Revert "kasli/opticlock: use plain ttls for channels 8-23" 
This reverts commit bd5c222569eb68d624a5ac1e9f2542f6ee553f83.

No decrease in power consumption or improvement in timing.
 2018-03-06 14:27:19 +01:00
Robert Jördens fd3cdce59a kasli/opticlock: use plain ttls for channels 8-23 2018-03-06 14:27:19 +01:00
Robert Jördens 956098c213 kasli: add second urukul, make clk_sel drive optional 2018-03-06 14:26:27 +01:00
Robert Jördens 07de7af86a kasli: make second eem optional in urukul 2018-03-06 14:26:26 +01:00
Sebastien Bourdeauducq a9daaad77b kasli: add SYSU variant and device_db 2018-03-02 14:44:31 +08:00
Sebastien Bourdeauducq 386aa75aaa kasli: control SFP1 and SFP2 LEDs in DRTIO satellite to match master 2018-02-27 23:18:18 +08:00
Sebastien Bourdeauducq 5d81877b34 kasli: implement multi-link DRTIO on SFP1 and SFP2 of master 2018-02-27 23:15:20 +08:00
Sebastien Bourdeauducq e565d3fa59 kasli: add analyzer and RTIO log to DRTIO master target 2018-02-27 18:09:07 +08:00
Robert Jördens 1452cd7447 novogorny: add coredevice driver and test with Kasli 
m-labs/artiq#687
 2018-02-22 17:19:51 +01:00
Robert Jördens 3b7971d15d kasli: spelling 2018-02-22 17:19:51 +01:00
Sebastien Bourdeauducq fa0d929b4d drtio: reorganize RX synchronizers 2018-02-22 15:21:23 +08:00
Sebastien Bourdeauducq e5de5ef473 kasli: use deterministic RX synchronizer 
Could not reproduce the "fully broken bitstream" bug.
 2018-02-22 15:18:09 +08:00
Robert Jördens a63fd306af urukul: use spi2 
* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
 2018-02-21 15:00:28 +00:00
Robert Jördens 91a4a7b0ee kasli: free run si5324 on opticlock for now 2018-02-21 13:37:29 +00:00
Robert Jördens 7e02d8245c kasli: false paths 
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
  ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
 2018-02-19 13:05:11 +00:00
Sebastien Bourdeauducq c329c83676 kasli: fix disable_si5324_ibuf no_retiming 2018-02-19 12:19:05 +08:00
Sebastien Bourdeauducq a93decdef2 kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized 2018-02-19 00:48:37 +08:00
Sebastien Bourdeauducq 83abdd283a drtio: signal stable clock input to transceiver 2018-02-18 22:29:30 +08:00
Sebastien Bourdeauducq 039dee4c8e si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER 
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
 2018-02-17 13:54:50 +08:00
Sebastien Bourdeauducq cfb21ca126 si5324: fix usage of external CLKIN2 reference 2018-02-17 13:52:01 +08:00
Robert Jördens e41f49cc75 kasli: opticlock 125 MHz, mark external reference case broken 2018-02-16 17:23:15 +00:00
Sebastien Bourdeauducq 4d42df2a7c kasli: set up Si5324 in standalone operation 2018-02-15 20:32:58 +08:00