Commit Graph

350 Commits

Author SHA1 Message Date
Donald Sebastian Leung e117fad73d Add RV64M Standard Extension 2020-08-28 12:20:56 +08:00
Donald Sebastian Leung 9b4644e905 Add REMUW instruction 2020-08-28 12:04:51 +08:00
Donald Sebastian Leung 64964655ff Add REMW instruction 2020-08-28 12:01:00 +08:00
Donald Sebastian Leung f1a5da1a34 Add DIVUW instruction 2020-08-28 11:55:11 +08:00
Donald Sebastian Leung b9f96a8ad0 Add DIVW instruction 2020-08-28 11:52:09 +08:00
Donald Sebastian Leung 1eab79538a Add MULW instruction 2020-08-28 11:45:45 +08:00
Donald Sebastian Leung 8fa2a33ecf Add RV64M R-Type Instruction 2020-08-28 11:37:54 +08:00
Donald Sebastian Leung 5d17b917b4 Update README.md 2020-08-27 16:25:54 +08:00
Donald Sebastian Leung fe5e73b6cb Add RV64I Base ISA 2020-08-27 16:21:53 +08:00
Donald Sebastian Leung e7066b8c89 Add SRAW instruction 2020-08-27 16:04:00 +08:00
Donald Sebastian Leung d188b9cdac Add SRLW instruction 2020-08-27 15:56:36 +08:00
Donald Sebastian Leung b60b590fe1 Add SLLW instruction 2020-08-27 15:54:01 +08:00
Donald Sebastian Leung 956be6570d Add SUBW instruction 2020-08-27 15:50:30 +08:00
Donald Sebastian Leung 2055f5159b Add ADDW instruction 2020-08-27 15:48:11 +08:00
Donald Sebastian Leung 6e4ecdcee0 Add RV64I R-Type Instruction 2020-08-27 15:39:09 +08:00
Donald Sebastian Leung cf295596ef Update README.md 2020-08-27 13:53:49 +08:00
Donald Sebastian Leung ade3d46b5b Add SRAIW instruction 2020-08-27 13:52:20 +08:00
Donald Sebastian Leung 94c19ed7f7 Add SRLIW instruction 2020-08-27 13:42:38 +08:00
Donald Sebastian Leung d837f6f8f6 Add SLLIW instruction 2020-08-27 13:39:11 +08:00
Donald Sebastian Leung 2790cb1f4c Add RV64I I-Type Instruction (Shift Variation) 2020-08-27 13:28:29 +08:00
Donald Sebastian Leung a15e57e12e Update README.md 2020-08-27 13:12:23 +08:00
Donald Sebastian Leung 3a332c5c1d Add ADDIW instruction 2020-08-27 13:11:23 +08:00
Donald Sebastian Leung dae95900b6 Update README.md 2020-08-27 12:54:28 +08:00
Donald Sebastian Leung 0954ee7fa9 Add SD instruction 2020-08-27 12:53:07 +08:00
Donald Sebastian Leung 472e0a70f8 Update README.md 2020-08-27 12:30:57 +08:00
Donald Sebastian Leung 94da2671dc Add LD instruction 2020-08-27 12:28:19 +08:00
Donald Sebastian Leung bd76a47a52 Add LWU instruction 2020-08-27 12:25:19 +08:00
Donald Sebastian Leung 92e34efe0d Add RV64I I-Type Instruction (Load Variation) 2020-08-27 12:20:17 +08:00
Donald Sebastian Leung 0af1f20423 Add RV64I I-Type Instruction 2020-08-27 11:46:04 +08:00
Donald Sebastian Leung fe835e272d Replace RV32I with RV32M for Minerva verification tasks 2020-08-27 10:48:35 +08:00
Donald Sebastian Leung 1ea25a4886 Add RV32M Standard Extension 2020-08-27 10:32:49 +08:00
Donald Sebastian Leung 3f3ec597a1 Update README.md 2020-08-26 17:21:27 +08:00
Donald Sebastian Leung 46e6ca3f70 Add REMU instruction 2020-08-26 17:15:27 +08:00
Donald Sebastian Leung fb91df7bb8 Add REM instruction 2020-08-26 17:11:03 +08:00
Donald Sebastian Leung 33ace9147a Add DIVU instruction 2020-08-26 17:03:49 +08:00
Donald Sebastian Leung 0708f6b962 Add DIV instruction 2020-08-26 16:58:50 +08:00
Donald Sebastian Leung b74a0cf699 Add MULHU instruction 2020-08-26 16:43:21 +08:00
Donald Sebastian Leung a58842ea94 Add MULHSU instruction 2020-08-26 16:39:17 +08:00
Donald Sebastian Leung 15580a74c6 Add MULH instruction 2020-08-26 16:30:54 +08:00
Donald Sebastian Leung 585965ee0a Add MUL instruction 2020-08-26 15:57:32 +08:00
Donald Sebastian Leung dd17606902 Add RV32M R-Type Instruction 2020-08-26 15:48:55 +08:00
Donald Sebastian Leung 3030839c42 Update README.md 2020-08-25 13:38:31 +08:00
Donald Sebastian Leung d1d93a6b6a Update README.md 2020-08-25 13:17:16 +08:00
Donald Sebastian Leung 83e65e50c5 Fix broken README 2020-08-25 12:43:13 +08:00
Donald Sebastian Leung ca9e9c9ca6 Add prototype for instruction/data bus implementation 2020-08-25 12:41:30 +08:00
Donald Sebastian Leung ac7991ae86 Merge instruction and data bus abstractions 2020-08-25 10:12:02 +08:00
Donald Sebastian Leung ca135d024f Wire instruction and data buses (WIP) to Minerva core 2020-08-24 14:46:52 +08:00
Donald Sebastian Leung 2a4f6dd07e Wire interrupt signals to Minerva for verification 2020-08-24 13:28:33 +08:00
Donald Sebastian Leung ee80bff3db Merge riscv_formal_parameters.py into verify.py 2020-08-24 10:20:30 +08:00
Donald Sebastian Leung 607d82f27c Add "Known Issues" section to README 2020-08-21 16:58:33 +08:00