Sebastien Bourdeauducq
c22482787e
sayma_amc: fix syntax
2021-02-17 17:45:54 +08:00
Sebastien Bourdeauducq
6861d3ab33
remove WRPLL
2021-02-17 16:09:51 +08:00
Sebastien Bourdeauducq
e54dd08821
metlino,sayma: adapt to new EEM API
...
This also enables 4X SERDES TTLs.
2021-02-10 15:32:10 +08:00
Harry Ho
43ecb3fea6
sayma: add comments about CPLL line rate on KU GTH
2020-12-19 17:05:20 +08:00
Sebastien Bourdeauducq
ccdc741e73
sayma_amc: fix --sfp argument
2020-12-07 18:02:36 +08:00
Astro
002a71dd8d
build_soc: rename identifier_str to gateware_identifier_str
2020-09-02 00:00:57 +08:00
Harry Ho
dfbf3311cb
sayma_amc: add support for 4x DIO output channels via FMC
2020-08-31 16:21:45 +08:00
Astro
45ae6202c0
build_soc: add identifier_str override option
...
Signed-off-by: Stephan Maka <stephan@spaceboyz.net>
2020-08-31 11:48:58 +08:00
Sebastien Bourdeauducq
d8b5bcf019
sayma_amc: support uTCA backplane for DRTIO
2020-05-29 14:58:49 +08:00
Sebastien Bourdeauducq
8b939b7cb3
sayma_amc: remove Master (obsoleted by Metlino)
2020-05-29 14:40:49 +08:00
Sebastien Bourdeauducq
ec7b2bea12
sayma: round FTW like Urukul in JDCGSyncDDS
2020-04-08 15:00:33 +08:00
Sebastien Bourdeauducq
0f4be22274
sayma: add simple sychronized DDS for testing
2020-04-08 14:13:54 +08:00
Sebastien Bourdeauducq
ffd3172e02
sayma: move SYSREF DDMTD to RTM ( #795 )
2020-04-06 00:01:28 +08:00
Sebastien Bourdeauducq
6d26def3ce
sayma: drive filtered_clk_sel on master variant
2020-02-06 22:28:49 +08:00
Sebastien Bourdeauducq
2b5213b013
wrpll: constrain clocks
2019-12-09 12:26:44 +08:00
Sebastien Bourdeauducq
46a776d06e
sayma: introduce WRPLL on RTM
2019-12-08 15:30:00 +08:00
Sebastien Bourdeauducq
eb271f383b
wrpll: add DDMTD cores
2019-11-28 22:03:50 +08:00
Sebastien Bourdeauducq
354d82cfe3
wrpll: drive helper clock domain
2019-11-28 17:40:00 +08:00
Sebastien Bourdeauducq
68cab5be8c
si549: cleanups
2019-11-28 16:36:59 +08:00
Sebastien Bourdeauducq
4832bfb08c
wrpll: i2c functions, select_recovered_clock placeholder
2019-11-27 21:21:00 +08:00
Sebastien Bourdeauducq
c536f6c4df
sayma_amc: output ddmtd_rec_clk
2019-11-20 19:16:04 +08:00
Sebastien Bourdeauducq
fe0c324b38
sayma: integrate si549 core
2019-11-20 17:37:16 +08:00
Sebastien Bourdeauducq
98854473dd
sayma_amc: use all transceivers on master ( #1230 )
2019-11-02 12:12:32 +08:00
Sebastien Bourdeauducq
228e44a059
sayma: enable Ethernet on DRTIO satellite variant
...
So that netboot can be used in bootloader.
2019-10-30 21:39:00 +08:00
Sebastien Bourdeauducq
dc71039934
sayma, metlino: increase integrated_sram_size on Ethernet-enabled variants
2019-10-30 21:36:00 +08:00
Sebastien Bourdeauducq
8fa3c6460e
sayma_amc: set direction of external TTL buffer according to RTIO PHY OE
2019-10-16 18:48:50 +08:00
Sebastien Bourdeauducq
21a1c6de3f
sayma: use SFP0 for DRTIO master
2019-10-16 17:53:40 +08:00
Sebastien Bourdeauducq
4df2c5d1fb
sayma: prepare for SYSREF align
...
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
2019-10-08 12:30:47 +08:00
Sebastien Bourdeauducq
03007b896e
sayma_amc: sma -> mcx
2019-10-07 20:31:35 +08:00
Sebastien Bourdeauducq
f62dc7e1d4
sayma: refactor JESD DAC channel groups
2019-10-06 20:15:09 +08:00
Sebastien Bourdeauducq
1c6c22fde9
sayma_amc: HMC830_REF moved to RTM side
2019-10-06 18:15:37 +08:00
Sebastien Bourdeauducq
e6ff44301b
sayma_amc: cleanup (v2.0 only)
2019-10-06 18:11:43 +08:00
Sebastien Bourdeauducq
e9b81f6e33
remove serwb
...
DRTIO is a better solution
2019-10-06 18:10:23 +08:00
Sebastien Bourdeauducq
7b95814cf5
sayma_amc: refactor, add SimpleSatellite variant
2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq
58b7bdcecc
sayma_amc: refactor RTM FPGA code
2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq
96fc4a21e8
sayma_amc: remove dummy FPGA pin assignment testing code
2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq
6cb0f5de59
sayma_amc: enable DRTIO switching
2019-10-04 22:55:23 +08:00
Sebastien Bourdeauducq
0cf8a46bbd
sayma_amc2: select filtered clock from Si5324
2019-10-04 21:28:26 +08:00
Sebastien Bourdeauducq
43e58c939c
sayma: drop MasterDAC
...
This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties.
Now Sayma works fine with Kasli as a master, which is simpler.
2019-06-14 14:06:16 +08:00
Sebastien Bourdeauducq
b04e15741b
drop SI5324_SAYMA_REF
2019-06-14 14:03:48 +08:00
Sebastien Bourdeauducq
cdef50c0dd
sayma_amc: Urukul v1.3
2019-05-19 16:54:38 +08:00
Sebastien Bourdeauducq
97b7ed557b
sayma_amc: do not use SFP0 (now used for Ethernet)
2019-04-12 18:47:18 +08:00
Sebastien Bourdeauducq
560849e693
sayma_amc: add DRTIO transceiver on rtm_amc_link for v2 hardware
2019-03-23 13:41:22 +08:00
Sebastien Bourdeauducq
bbb8c00518
sayma_amc: default to satellite variant
2019-03-23 13:37:55 +08:00
Sebastien Bourdeauducq
33b28f6e56
sayma_amc: add placeholder code to use DDMTD signals on v2 hardware
2019-03-21 17:37:22 +08:00
Sebastien Bourdeauducq
2ec5a58c59
sayma_amc: si5324_clkout -> cdr_clk_clean
2019-03-21 14:09:33 +08:00
Sebastien Bourdeauducq
62c7f75a9e
sayma_amc: support hardware revisions
2019-02-25 23:49:45 +08:00
Sebastien Bourdeauducq
d45249197c
siphaser: improve ultrascale clock routing
2019-02-25 23:00:01 +08:00
Sebastien Bourdeauducq
ec230d6560
sayma: move SYSREF DDMTD to the RTM
...
Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
2019-01-31 20:39:33 +08:00
Sebastien Bourdeauducq
9ae57fd51e
sayma: pass rtio_clk_freq to DDMTD core
2019-01-29 15:06:45 +08:00
