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sayma: introduce WRPLL on RTM
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f35f658bc5
commit
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@ -1 +1,2 @@
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from artiq.gateware.drtio.wrpll.core import WRPLL
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from artiq.gateware.drtio.wrpll.ddmtd import DDMTDSamplerExtFF, DDMTDSamplerGTP
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@ -23,19 +23,5 @@ class WRPLL(Module, AutoCSR):
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ddmtd_counter = Signal(N)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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if hasattr(ddmtd_inputs, "rec_clk"):
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ddmtd_input_rec_clk = ddmtd_inputs.rec_clk
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else:
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ddmtd_input_rec_clk = Signal()
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self.specials += Instance("IBUFDS",
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i_I=ddmtd_inputs.rec_clk_p, i_IB=ddmtd_inputs.rec_clk_n,
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o_O=ddmtd_input_rec_clk)
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if hasattr(ddmtd_inputs, "main_xo"):
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ddmtd_input_main_xo = ddmtd_inputs.main_xo
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else:
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ddmtd_input_main_xo = Signal()
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self.specials += Instance("IBUFDS",
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i_I=ddmtd_inputs.main_xo_p, i_IB=ddmtd_inputs.main_xo_n,
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o_O=ddmtd_input_main_xo)
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_input_rec_clk)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_input_main_xo)
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
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@ -3,6 +3,47 @@ from migen.genlib.cdc import PulseSynchronizer, MultiReg
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from misoc.interconnect.csr import *
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class DDMTDSamplerExtFF(Module):
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def __init__(self, ddmtd_inputs):
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# TODO: s/h timing at FPGA pads
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if hasattr(ddmtd_inputs, "rec_clk"):
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self.rec_clk = ddmtd_inputs.rec_clk
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else:
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self.rec_clk = Signal()
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self.specials += Instance("IBUFDS",
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i_I=ddmtd_inputs.rec_clk_p, i_IB=ddmtd_inputs.rec_clk_n,
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o_O=self.rec_clk)
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if hasattr(ddmtd_inputs, "main_xo"):
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self.main_xo = ddmtd_inputs.main_xo
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else:
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self.main_xo = Signal()
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self.specials += Instance("IBUFDS",
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i_I=ddmtd_inputs.main_xo_p, i_IB=ddmtd_inputs.main_xo_n,
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o_O=self.main_xo)
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class DDMTDSamplerGTP(Module):
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def __init__(self, gtp, main_xo_pads):
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self.rec_clk = Signal()
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self.main_xo = Signal()
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# Getting this signal from IBUFDS_GTE2 is problematic because:
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# 1. the clock gets divided by 2
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# 2. the transceiver PLL craps out if an improper clock signal is applied,
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# so we are disabling the buffer until the clock is stable.
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# 3. UG482 says "The O and ODIV2 outputs are not phase matched to each other",
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# which may or may not be a problem depending on what it actually means.
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main_xo_se = Signal()
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self.specials += Instance("IBUFDS",
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i_I=main_xo_pads.p, i_IB=main_xo_pads.n,
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o_O=main_xo_se)
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self.sync.helper += [
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self.rec_clk.eq(gtp.cd_rtio_rx0.clk),
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self.main_xo.eq(main_xo_se)
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]
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class DDMTDEdgeDetector(Module):
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def __init__(self, input_signal):
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self.rising = Signal()
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@ -19,7 +19,7 @@ from artiq.gateware import jesd204_tools
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_ultrascale, sawg
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.wrpll import WRPLL
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from artiq.gateware.drtio.wrpll import WRPLL, DDMTDSamplerExtFF
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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@ -136,11 +136,13 @@ class SatelliteBase(MiniSoC):
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platform.request("ddmtd_main_dcxo_oe").eq(1),
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platform.request("ddmtd_helper_dcxo_oe").eq(1)
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]
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self.submodules.wrpll_sampler = DDMTDSamplerExtFF(
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platform.request("ddmtd_inputs"))
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self.submodules.wrpll = WRPLL(
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helper_clk_pads=platform.request("ddmtd_helper_clk"),
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main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
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ddmtd_inputs=platform.request("ddmtd_inputs"))
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ddmtd_inputs=self.wrpll_sampler)
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self.csr_devices.append("wrpll")
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else:
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self.comb += platform.request("filtered_clk_sel").eq(1)
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@ -19,6 +19,7 @@ from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_serdes_7series
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.wrpll import WRPLL, DDMTDSamplerGTP
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import add_identifier
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@ -73,7 +74,7 @@ class _SatelliteBase(BaseSoC):
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq, **kwargs):
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def __init__(self, rtio_clk_freq, *, with_wrpll, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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**kwargs)
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@ -132,21 +133,37 @@ class _SatelliteBase(BaseSoC):
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ref_clk=self.crg.cd_sys.clk, ref_div2=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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if with_wrpll:
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self.comb += [
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platform.request("filtered_clk_sel").eq(0),
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platform.request("ddmtd_main_dcxo_oe").eq(1),
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platform.request("ddmtd_helper_dcxo_oe").eq(1)
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]
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self.submodules.wrpll_sampler = DDMTDSamplerGTP(
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self.drtio_transceiver,
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platform.request("cdr_clk_clean_fabric"))
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self.submodules.wrpll = WRPLL(
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helper_clk_pads=platform.request("ddmtd_helper_clk"),
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main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
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ddmtd_inputs=self.wrpll_sampler)
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self.csr_devices.append("wrpll")
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else:
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ref_clk=self.crg.cd_sys.clk, ref_div2=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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gtp = self.drtio_transceiver.gtps[0]
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@ -245,10 +262,12 @@ def main():
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soc_sayma_rtm_args(parser)
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parser.add_argument("--rtio-clk-freq",
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default=150, type=int, help="RTIO clock frequency in MHz")
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parser.add_argument("--with-wrpll", default=False, action="store_true")
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parser.set_defaults(output_dir=os.path.join("artiq_sayma", "rtm"))
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args = parser.parse_args()
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soc = Satellite(rtio_clk_freq=1e6*args.rtio_clk_freq,
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soc = Satellite(
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rtio_clk_freq=1e6*args.rtio_clk_freq, with_wrpll=args.with_wrpll,
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**soc_sayma_rtm_argdict(args))
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builder = SatmanSoCBuilder(soc, **builder_argdict(args))
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try:
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