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141 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 47312e55d3 sayma: set RTIO_FREQUENCY in MasterDAC 2019-01-28 13:43:28 +08:00
Sebastien Bourdeauducq 443d6d8688 sayma_amc: pass RTIO clock frequency to SiPhaser 2019-01-28 09:49:03 +08:00
Sebastien Bourdeauducq 9966e789fc sayma: simplify Ultrascale LVDS T false path 
Recommended by Xilinx.
 2019-01-25 23:40:48 +08:00
Sebastien Bourdeauducq 359fb1f207 sayma: fix DDMTD STA 2019-01-25 23:39:19 +08:00
Sebastien Bourdeauducq cb04230f86 sayma: SYSREF setup/hold validation demonstration 
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
 2019-01-25 16:58:58 +08:00
Sebastien Bourdeauducq 3356717316 sayma: DDMTD SYSREF measurement demonstration 2019-01-25 16:00:31 +08:00
Sebastien Bourdeauducq 4941fb3300 sayma: 2.4GHz DAC clocking (4X interpolation) 
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
 2019-01-25 13:47:04 +08:00
Sebastien Bourdeauducq a2ff2cc173 sayma_amc: use more selective IOBUFDS false path 2019-01-19 11:47:50 +08:00
Sebastien Bourdeauducq 4cb9f77fd8 sayma_amc: fix Master timing constraints 2019-01-13 13:53:07 +08:00
Sebastien Bourdeauducq 9b213b17af sayma_amc: forward RTM UART in Master variant as well 2019-01-09 18:57:57 +08:00
Sebastien Bourdeauducq c7b18952b8 sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad 2019-01-09 13:47:08 +08:00
Sebastien Bourdeauducq 66b3132c28 sayma_amc: fix RTIO TSC instantiation 2019-01-06 14:54:32 +08:00
Sebastien Bourdeauducq 2100a8b1f1 sayma_amc: more fighting with vivado timing analyzer 2019-01-05 12:25:30 +08:00
Sebastien Bourdeauducq 62d7c89c48 sayma_amc: use high-resolution TTL on SMAs (#792) 2019-01-03 20:50:38 +08:00
Sebastien Bourdeauducq 175f8b8ccc drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT (#792) 2019-01-03 20:14:18 +08:00
Sebastien Bourdeauducq cc58318500 siphaser: autocalibrate skew using RX synchronizer 
* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
 2019-01-02 22:29:27 +08:00
Sebastien Bourdeauducq f5cda3689e sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant 2019-01-02 16:46:16 +08:00
Sebastien Bourdeauducq 73f0de7c79 sayma: DRTIO master fixes 2018-09-20 11:15:45 +08:00
Sebastien Bourdeauducq 87e0384e97 drtio: separate aux controller 
This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
 2018-09-05 17:56:58 +08:00
Sebastien Bourdeauducq 1450e17a73 sayma: adapt to TSC and DRTIOSatellite changes 2018-09-05 12:10:41 +08:00
Sebastien Bourdeauducq 167e97efd2 sayma: support external RTM clocking 2018-08-17 22:57:54 +08:00
Sebastien Bourdeauducq 49f7a1610f sayma: use GTP_CLK1 only for all variants (#1080) 2018-08-07 20:53:14 +08:00
Sebastien Bourdeauducq b023865b42 sayma: instantiate dummy IBUFDS_GTE3 on unused but driven Si5324 clock pins 
Solve same problem as e83ee3a0 but channels cannot be independently disabled.
 2018-08-05 23:02:41 +08:00
Sebastien Bourdeauducq e83ee3a07a hmc7043: disable GTP_CLK1 when not in use 
Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is
not instantiated, and driving a clock then leads to overvoltage.
 2018-08-03 10:03:52 +08:00
Sebastien Bourdeauducq 25170a53e5 sayma: add back Urukul and Zotino 2018-07-18 10:27:54 +08:00
Sebastien Bourdeauducq 4fdc20bb11 sayma: disable Urukul and Zotino for now 
Ultrascale I/Os are being a pain as usual and the SPI core won't compile.
 2018-07-17 20:08:21 +08:00
Sebastien Bourdeauducq d724bd980c sayma: add EEMs to Master 2018-07-17 18:58:23 +08:00
Sebastien Bourdeauducq 3645a6424e sayma: fix Master build 2018-07-17 18:56:33 +08:00
Sebastien Bourdeauducq b2695d03ed sayma: remove with_sawg from Master variant 2018-07-15 17:38:29 +08:00
Sebastien Bourdeauducq b27fa8964b add variant in identifier string 
Also add without-sawg suffixes on Sayma.

Closes #1060
Closes #1059
 2018-07-15 17:21:17 +08:00
Sebastien Bourdeauducq 729ce58f98 sayma: use GTP_CLK1 to clock DRTIO satellite transceiver 
This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.

Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.
 2018-06-28 11:23:40 +08:00
Sebastien Bourdeauducq a65721d649 sayma: put RTM clock tree into the siphaser loop 
* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
 2018-06-27 21:46:55 +08:00
Sebastien Bourdeauducq c750de2955 sayma: add many-port pure DRTIO master 2018-06-25 18:21:22 +08:00
Sebastien Bourdeauducq 68530fde07 sayma: generate 100MHz from Si5324 on standalone and master targets 
* Allow switching between DRTIO satellite and standalone without
  touching the hardware.
* Allow operating standalone and master without an additional RF
  signal generator.
 2018-06-23 10:44:38 +08:00
Sebastien Bourdeauducq 60b22217ce sayma: set DRTIO master HMC830_REF to 100MHz 2018-06-22 10:10:09 +08:00
Sebastien Bourdeauducq e6d1726754 sayma: add RTIO log to DRTIO master 2018-06-22 00:05:22 +08:00
Sebastien Bourdeauducq 83428961ad sayma: add SAWG and JESD to DRTIO master 2018-06-22 00:04:22 +08:00
Sebastien Bourdeauducq 8b3c12e6eb sayma: clock DRTIO master transceiver from HMC7043 2018-06-21 22:34:44 +08:00
Sebastien Bourdeauducq b28ff587c5 sayma: add sysref sampler to DRTIO master 2018-06-21 22:28:34 +08:00
Sebastien Bourdeauducq 28fb0fd754 sayma: add SYSREF sampler gateware 2018-06-20 17:48:35 +08:00
Sebastien Bourdeauducq 75b6cea52f sayma: add SAWG to DRTIO satellite 2018-06-19 19:12:10 +08:00
Sebastien Bourdeauducq 433273dd95 sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite 2018-06-19 14:33:48 +08:00
Sebastien Bourdeauducq 6403a0d5d1 sayma_amc: update without-sawg description 2018-06-19 13:52:05 +08:00
Sebastien Bourdeauducq d29b3dd588 hmc830: compile-time configurable reference frequency 2018-06-19 13:47:32 +08:00
Robert Jördens 32484a62de sayma_amc: remove unused imports 2018-06-17 13:09:44 +02:00
Robert Jördens 53ab255c00 sayma_amc: enable slave fpga loading (#813) 2018-06-16 12:47:26 +02:00
Robert Jördens a143e238a8 savel_fpga: get rid of unneeded config 2018-06-12 10:24:04 +02:00
Florent Kermarrec 89797d08ed serwb: revert to 125MHz linerate (until we understand why 1gbps version breaks between builds) 2018-06-07 15:13:56 +02:00
Florent Kermarrec 009db5eda9 serwb: revert 1gbps linerate 2018-06-06 16:20:20 +02:00
Robert Jördens e21b7965b9 sayma_amc: change test patterns for 'without-sawg' 2018-06-06 08:02:52 +00:00
Florent Kermarrec f8a9dd930b serwb/genphy: add device parameter (not used here, but this way all the phys share the same parameters), scrambling is also now always enabled. 2018-05-15 23:51:14 +02:00
Florent Kermarrec c18a73d45f sayma_amc/rtm: use new serwb low-speed phy 2018-05-15 16:40:50 +02:00
whitequark ee4c475cf3 gateware: fix Sayma satellite build. 
RTIO clock multiplier was removed from Sayma in 32f22f4c.
 2018-05-13 13:10:39 +00:00
Sebastien Bourdeauducq 6b811c1a8b sayma: fix runtime/rtm gateware address conflict 2018-05-09 19:47:29 +08:00
Florent Kermarrec 8212e46f5e sayma_amc: filter jesd refclk/sysref with jreset (hmc7043 can generate noise when unconfigured see sinara issue #541) 2018-04-27 13:04:37 +02:00
Florent Kermarrec 439d2bf2bc sayma/serwb: adapt, full reset of rtm on link reset 2018-04-17 19:24:03 +02:00
Florent Kermarrec 1acd7ea1db sayma/serwb: re-enable scrambling 2018-04-17 00:49:36 +02:00
Florent Kermarrec ca01c8f1cb sayma: reduce serwb linerate to 500Mbps 2018-04-16 23:19:15 +02:00
Florent Kermarrec bb90fb7d59 sayma/serwb: remove scrambling (does not seems to work on sayma for now...) 2018-04-07 15:57:57 +02:00
Florent Kermarrec e15f8aa903 sayma/serwb: enable scrambling 2018-04-07 14:52:37 +02:00
Florent Kermarrec 73b727cade serwb: new version using only sys/sys4x clocks domains, scrambling deactivated. 2018-04-07 02:59:14 +02:00
Florent Kermarrec aef0153a8f targets/sayma: adapt to new serwb clocking 2018-04-03 18:53:39 +02:00
Sebastien Bourdeauducq 493d2a653f siphaser: add false path between sys_clk and mmcm_freerun_output 2018-03-29 10:55:41 +08:00
Sebastien Bourdeauducq 3d89ba2e11 sayma: remove debug leftover 2018-03-29 10:20:17 +08:00
Sebastien Bourdeauducq 32f22f4c9c sayma: disable SERDES TTL entirely 
Timing closure becomes very random, even at 4X.
 2018-03-21 13:03:48 +08:00
Sebastien Bourdeauducq f8c2d54e75 ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma 2018-03-21 13:01:38 +08:00
Sebastien Bourdeauducq 9c2d343052 sayma: use SERDES RTIO TTL 
This is not enabled on the standalone design as it breaks timing.
 2018-03-21 10:53:52 +08:00
Sebastien Bourdeauducq fc3d97f1f7 drtio: remove spurious multichannel transceiver clock constraints 
They used to cause (otherwise harmless) Vivado critical warnings.
 2018-03-09 22:46:27 +08:00
Sebastien Bourdeauducq 916197c4d7 siphaser: cleanup 2018-03-07 11:15:44 +08:00
Sebastien Bourdeauducq 7d98864b31 sayma: enable siphaser 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq a6e29462a8 sayma: enable multilink DRTIO 2018-03-07 10:57:30 +08:00
Robert Jördens 994ceca9ff sayma_amc: disable slave fpga gateware loading 2018-03-06 17:27:43 +01:00
Robert Jördens ddcc68cff9 sayma_amc: move bitstream options to migen 
close #930
 2018-03-02 18:13:03 +08:00
Robert Jördens 54984f080b artiq_flash: flash RTM firmware 
based on whitequark's work in f95fb27

m-labs/artiq#813
 2018-02-28 19:29:01 +01:00
Robert Jördens 1f999c7f5f sayma_amc: expose RTM fpga load pins as GPIOs 2018-02-28 18:44:36 +01:00
Sebastien Bourdeauducq fa0d929b4d drtio: reorganize RX synchronizers 2018-02-22 15:21:23 +08:00
Sebastien Bourdeauducq 0f4549655b sayma: use Xilinx RX synchronizer 
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
 2018-02-19 17:49:53 +08:00
Sebastien Bourdeauducq 3bc575bee7 drtio: add missing define for Sayma master 2018-02-19 17:11:21 +08:00
Sebastien Bourdeauducq 7376ab0ff8 drtio: fix Sayma after 83abdd28 2018-02-19 17:10:55 +08:00
Sebastien Bourdeauducq 287d533437 Revert "sayma_amc: remove RTM bitstream upload core. Closes #908" 
This reverts commit 2d4a1340ea.
 2018-02-17 17:38:48 +08:00
Sebastien Bourdeauducq 73985a9215 sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed) 2018-02-17 17:38:17 +08:00
Sebastien Bourdeauducq 039dee4c8e si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER 
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
 2018-02-17 13:54:50 +08:00
Sebastien Bourdeauducq 2d4a1340ea sayma_amc: remove RTM bitstream upload core. Closes #908 2018-02-07 12:27:35 +08:00
whitequark 885ab40946 conda: split RTM and AMC packages back. 
This avoids multiplying the RTM compilation time by the number
of AMC packages.
 2018-01-28 14:27:55 +00:00
whitequark 11a8b84355 Merge the build trees of sayma_amc and sayma_rtm targets. 
This also makes them a single artiq_flash target, and a single
conda package.
 2018-01-27 19:54:31 +00:00
Robert Jördens e0e795f11c sayma_amc: constrain pin, remove keep 2018-01-23 15:42:47 +00:00
Sebastien Bourdeauducq 4b4374f76a sayma: register_jref for JESD204. Closes #904 2018-01-23 12:19:15 +08:00
Sebastien Bourdeauducq 296ac35f5d sayma_amc: SFP TX disable is active-high 2018-01-23 00:32:09 +08:00
Sebastien Bourdeauducq ab7c49d6d0 sayma_amc: raise error on invalid variant 2018-01-23 00:02:16 +08:00
Sebastien Bourdeauducq 53facfef13 sayma: build fixes 2018-01-22 18:33:22 +08:00
Sebastien Bourdeauducq 25f3feeda8 refactor targets 2018-01-22 18:25:10 +08:00