M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-28 20:53:35 +08:00
Code Issues Projects Releases Wiki Activity

sayma_amc: output ddmtd_rec_clk

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2019-11-20 19:16:04 +08:00
parent ae50da09c4
commit c536f6c4df
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
artiq/gateware/targets/sayma_amc.py
View File

@ -66,6 +66,10 @@ class SatelliteBase(MiniSoC):
platform = self.platform
if with_wrpll:
clock_recout_pads = platform.request("ddmtd_rec_clk")
else:
clock_recout_pads = None
# Use SFP0 to connect to master (Kasli)
self.comb += platform.request("sfp_tx_disable", 0).eq(0)
drtio_data_pads = [
@ -76,7 +80,8 @@ class SatelliteBase(MiniSoC):
clock_pads=platform.request("cdr_clk_clean"),
data_pads=drtio_data_pads,
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
rtio_clk_freq=rtio_clk_freq,
clock_recout_pads=clock_recout_pads)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)