M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-29 05:03:34 +08:00
Code Issues Projects Releases Wiki Activity

sayma, metlino: increase integrated_sram_size on Ethernet-enabled variants

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2019-10-30 21:36:00 +08:00
parent 3042476230
commit dc71039934
2 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
artiq/gateware/targets/metlino.py
View File

@ -43,6 +43,7 @@ class Master(MiniSoC, AMPSoC):
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)

1
artiq/gateware/targets/sayma_amc.py
View File

@ -340,6 +340,7 @@ class Master(MiniSoC, AMPSoC):
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)