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1528 Commits

Author SHA1 Message Date
Spaqin 35f30ddf05
Expose TTLClockGen for Kasli JSONs (#1886) 2022-05-06 13:33:42 +08:00
Leon Riesebos c4292770f8
Kasli JSON description for SPI over DIO cards (#1800) 2022-02-26 07:36:00 +08:00
Peter Drmota 4eee49f889 gateware.test.suservo: Fix tests for python >=3.7 
Closes #1748
 2022-01-11 17:16:09 +08:00
occheung 9eee0e5a7b gateware/suservo: fix profile no. in test 
Follow-up/Test update for 9d49302.
 2022-01-11 14:20:47 +08:00
occheung cea0a15e1e suservo: use default urukul profile 2022-01-10 16:21:39 +08:00
occheung 9d493028e5 gateware/suservo: write to profile 7 
Fixes #1817.
 2022-01-07 16:41:19 +08:00
mwojcik 7953f3d705 kc705: add drtio 100mhz clk switch 2021-12-03 17:19:11 +08:00
mwojcik f281112779 satman: add 100mhz si5324 settings 
siphaser: add calculated vco for 100mhz comment
 2021-12-03 17:19:11 +08:00
mwojcik eec3ea6589 siphaser: add support for 100mhz rtio 2021-12-03 17:19:11 +08:00
Etienne Wodey 9f830b86c0
kasli: add SED lanes count option to HW description JSON file (#1745) 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-12-03 17:05:35 +08:00
Peter Drmota 20e079a381
AD9910 driver feature extension and SUServo IIR readability (#1500) 
* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync

* SUServo: Wrap CPLD and DDS devices in a list

* SUServo: Refactor [nfc]

Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
 2021-11-15 12:09:16 +08:00
occheung 09945ecc4d gateware: fix drtio/dma tests 2021-11-08 16:59:08 +08:00
occheung cb247f235f gateware: pass adr_w/data_w to submodules 2021-11-08 16:59:08 +08:00
occheung 90f944481c kernel_cpu: add fpu if not kasli v1.x 2021-11-08 16:59:08 +08:00
occheung d84ad0095b comm_cpu: select 64b bus if not kasli v1.x 2021-11-08 16:59:08 +08:00
occheung dd68b4ab82 mailbox: parametrize address width 2021-11-08 16:59:08 +08:00
occheung c6e0e26440 drtio: accept 32b/64b bus 2021-11-08 16:59:08 +08:00
occheung 8da924ec0f dma: set conversion granularity using bus width 2021-11-08 16:59:08 +08:00
Robert Jördens 591507a7c0
Merge pull request #1774 from m-labs/fastino-cic 
Fastino cic
 2021-10-28 17:44:20 +02:00
Harry Ho 0aa8a739aa sayma_rtm: fix RTM firmware not in little-endian for RISC-V 2021-10-25 11:20:26 +08:00
Robert Jördens 3f6bf33298 fastino: add interpolator support 2021-10-08 15:47:07 +00:00
Spaqin 1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path (#1760) 2021-10-07 08:19:38 +08:00
occheung 051a14abf2 rtio/dma: fix endianness 2021-09-10 13:25:12 +08:00
occheung a833974b50 analyzer: fix endianness 2021-09-10 13:25:12 +08:00
occheung fc42d053d9 kernel: use vexriscv 2021-09-10 13:25:12 +08:00
occheung 1b516b16e2 targets: default to vexriscv cpu 2021-09-10 13:25:12 +08:00
Mikołaj Sowiński 898122f3e5
Added support for HVAMP_8CH (#1741) 2021-08-16 13:39:00 +08:00
mwojcik 7879d3630b made kc705/gtx interface more similar to kasli/gtp 2021-08-10 18:53:52 +08:00
Sebastien Bourdeauducq 242dfae38e kc705: fix DRTIO targets 2021-08-06 15:41:47 +08:00
Sebastien Bourdeauducq dc546630e4 kc705: DRTIO variants WIP 2021-08-06 14:41:41 +08:00
Robert Jördens fd824f7ad0 ddb_template: print LED channel nos on Kasli v2 2021-08-05 17:29:38 +02:00
Sebastien Bourdeauducq ea0c7b6173 Merge remote-tracking branch 'harrydrtio/k7-drtio' 2021-06-15 10:04:45 +08:00
Star Chen 9dee8bb9c9
Kasli: Added front panel user LED (#1623) (#1694) 2021-06-07 16:05:50 +08:00
Sebastien Bourdeauducq 92fd705990 increase memory allocated to comms CPU 
See discussion in #1612.
 2021-02-21 19:06:12 +08:00
Sebastien Bourdeauducq d33a206f04 eem: fix Urukul QSPI after 9ef5717de8 (2) 2021-02-12 13:17:48 +08:00
Sebastien Bourdeauducq 22ce5b0299 eem: fix Urukul QSPI after 9ef5717de8 2021-02-12 10:59:53 +08:00
Sebastien Bourdeauducq e54dd08821 metlino,sayma: adapt to new EEM API 
This also enables 4X SERDES TTLs.
 2021-02-10 15:32:10 +08:00
Sebastien Bourdeauducq 547254e89e eem_7series: pass through kwargs 2021-02-10 15:31:49 +08:00
Sebastien Bourdeauducq 49299c00a9 eem: enable DCI for LVDS TTL 2021-02-10 15:31:25 +08:00
Sebastien Bourdeauducq 9ef5717de8 eem: support different I/O standards in EEM slots 2021-02-10 15:31:05 +08:00
Astro 461199b903 kasli_generic: warn if min_artiq_version is not met 2021-02-10 15:26:15 +08:00
Sebastien Bourdeauducq cf9cf0ab6f ttl_serdes_7series: add dci (HP bank) support 2021-02-07 22:32:18 +08:00
Sebastien Bourdeauducq 997a48fb31 ttl_serdes_ultrascale: fix, add dummy dci argument 2021-02-07 22:31:46 +08:00
Sebastien Bourdeauducq bbe0c9162a ttl_serdes_ultrascale: cleanup 2021-02-07 22:00:33 +08:00
Sebastien Bourdeauducq 3572e2a9c7 ttl_serdes_7series: fix 2021-02-07 21:41:13 +08:00
Sebastien Bourdeauducq 88c212b84f ttl_serdes_7series: cleanup 2021-02-07 21:33:21 +08:00
Sebastien Bourdeauducq db25f4e8f7 ttl_serdes_7series: use simpler I/O buffers 
In theory equivalent with these parameters.
 2021-02-07 20:10:37 +08:00
Sebastien Bourdeauducq 6bd9691ba8 gateware: remove TTL dead code 2021-02-07 19:58:02 +08:00
Sebastien Bourdeauducq bfacd1e5b3 eem: fix Grabber cc_0-2 signal definitions 2021-02-07 18:01:05 +08:00
Sebastien Bourdeauducq f7a33a1f99 gateware: make 7-series EEM handling functions shareable 2021-02-07 14:34:26 +08:00