M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

ttl_serdes_7series: use simpler I/O buffers 

In theory equivalent with these parameters.
pull/1605/head
Sebastien Bourdeauducq 2021-02-07 20:10:37 +08:00
parent 6bd9691ba8
commit db25f4e8f7
1 changed files with 2 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
artiq/gateware/rtio/phy/ttl_serdes_7series.py
View File

@ -28,12 +28,7 @@ class _OSERDESE2_8X(Module):
if pad_n is None:
self.comb += pad.eq(pad_o)
else:
self.specials += Instance("IOBUFDS_INTERMDISABLE",
p_DIFF_TERM="FALSE",
p_IBUF_LOW_PWR="TRUE",
p_USE_IBUFDISABLE="TRUE",
i_IBUFDISABLE=1,
i_INTERMDISABLE=1,
self.specials += Instance("IOBUFDS",
i_I=pad_o,
i_T=self.t_out,
io_IO=pad, io_IOB=pad_n)
@ -63,12 +58,7 @@ class _ISERDESE2_8X(Module):
if pad_n is None:
self.comb += pad_i.eq(pad)
else:
self.specials += Instance("IBUFDS_INTERMDISABLE",
p_DIFF_TERM="TRUE",
p_IBUF_LOW_PWR="TRUE",
p_USE_IBUFDISABLE="TRUE",
i_IBUFDISABLE=0,
i_INTERMDISABLE=0,
self.specials += Instance("IBUFDS",
o_O=pad_i,
io_I=pad, io_IB=pad_n)