flake: update boot.bif to use elf_use_ph

On recv bytes through TCP conection, a heap buffer of dynamic size is allocated as the memory backing.

.gitignore

@@ -3,3 +3,11 @@ examples/*.elf
 __pycache__
 
 build
+
+src/libboard_artiq/Cargo.toml
+src/libc/Cargo.toml
+src/libdyld/Cargo.toml
+src/libio/Cargo.toml
+src/libksupport/Cargo.toml
+src/runtime/Cargo.toml
+src/satman/Cargo.toml

README.md

@@ -4,73 +4,107 @@ ARTIQ on Zynq
 How to use
 ----------
 
-1. Install ARTIQ-6 or newer.
-2. Select the latest successful build on Hydra: https://nixbld.m-labs.hk/jobset/artiq/zynq
-3. Search for the job named ``<board>-<variant>-sd`` (for example: ``zc706-nist_clock-sd`` or ``zc706-nist_qc2-sd``).
-4. Download the ``boot.bin`` "binary distribution" and place it at the root of a FAT-formatted SD card.
-5. Optionally, create a ``config.txt`` configuration file at the root of the SD card containing ``key=value`` pairs on each line. Use the ``ip``, ``ip6`` and ``mac`` keys to respectively set the IPv4, IPv6 and MAC address of the board. Configuring an IPv6 address is entirely optional. If these keys are not found, the firmware will use default values that may or may not be compatible with your network.
-6. Insert the SD card into the board and set up the board to boot from the SD card. For the ZC706, this is achieved by placing the large DIP switch SW11 in the 00110 position.
-7. Power up the board. After the firmware starts successfully, it should respond to ping at its IP addresses, and boot messages can be observed from its UART at 115200bps.
-8. Create and use an ARTIQ device database as usual, but set ``"target": "cortexa9"`` in the arguments of the core device.
+1. [Install ARTIQ](https://m-labs.hk/artiq/manual/installing.html). Get the corresponding version to the ``artiq-zynq`` version you are targeting.
+2. To obtain firmware binaries, use AFWS or build your own; see [the ARTIQ manual](https://m-labs.hk/artiq/manual/building_developing.html) for detailed instructions or skip to "Development" below. ZC706 variants only can also be downloaded from latest successful build on [Hydra](https://nixbld.m-labs.hk/).
+3. Place ``boot.bin`` file at the root ``/`` of a FAT-formatted SD card.
+4. Optionally, create a ``config.txt`` configuration file containing ``key=value`` pairs on each line and place it at the root of the SD card. See below for valid keys. The ``ip``, ``ip6`` and ``mac`` keys can be used to set networking information. If these keys are not found, the firmware will use default values which may or may not be compatible with your network.
+5. Insert the SD card into the board and set the board to boot from the SD card. For ZC706, this is achieved by placing the large DIP switch SW11 into the 00110 position. On Kasli-SoC, place the BOOT MODE switches to SD.
+6. Power up the board. After successful boot the firmware should respond to ping at its IP addresses. Boot output can be observed from UART at 115200bps 8-N-1.
+7. Create and use an ARTIQ device database as usual.
 
 Configuration
 -------------
 
-Configuring the device is done using the ``config.txt`` text file at the root of the SD card, plus the contents of the ``config`` folder. When searching for a configuration key, the firmware first looks for a file named ``/config/[key].bin`` and, if it exists, returns the contents of that file. If not, it looks into ``/config.txt``, which contains a list of ``key=value`` pairs, one per line. The ``config`` folder allows configuration values that consist in binary data, such as the startup kernel.
+Configuring the device is done using the ``config.txt`` text file at the root of the SD card plus optionally a ``config`` folder. When searching for a configuration key, the firmware first looks for a file named ``/config/[key].bin`` and, if it exists, returns the contents of that file. If not, it looks into ``/config.txt``, which should contain a list of ``key=value`` pairs, one per line. ``config.txt`` should be used for most keys but the ``config`` folder allows for setting configuration values which consist of binary data, such as the startup kernel.
 
-The following configuration keys are available:
+The following configuration keys are available among others:
 
 - ``mac``: Ethernet MAC address.
 - ``ip``: IPv4 address.
 - ``ip6``: IPv6 address.
-- ``startup``: startup kernel in ELF format (as produced by ``artiq_compile``).
-- ``rtioclk``: source of RTIO clock; valid values are ``external`` and ``internal``.
-- ``boot``: SD card "boot.bin" file, for replacing the boot firmware/gateware. Write only.
+- ``idle_kernel``: idle kernel in ELF format (as produced by ``artiq_compile``).
+- ``startup_kernel``: startup kernel in ELF format (as produced by ``artiq_compile``).
+- ``rtio_clock``: source of RTIO clock; valid values are ``ext0_bypass`` and ``int_125``.
 
-Configurations can be read/written/removed via ``artiq_coremgmt``. Config erase is
-not implemented as it seems not very useful.
+See [ARTIQ manual](https://m-labs.hk/artiq/manual-beta/core_device.html#configuration-storage) for full list. Configurations can be read/written/removed with ``artiq_coremgmt``. Config erase is not implemented, as it isn't particularly useful.
+
+For convenience, the ``boot`` key can be used with ``artiq_coremgmt`` and a ``boot.bin`` file to replace firmware/gateware in a running system. This key is read-only. When loading ``boot.bin`` onto the SD card directly, place it at the root and not in the ``config`` folder.
 
 Development instructions
 ------------------------
 
-Configure Nix channels:
+ARTIQ on Zynq is packaged using [Nix](https://nixos.org) Flakes. Install Nix 2.8+ and enable flakes by adding ``experimental-features = nix-command flakes`` to ``nix.conf`` (e.g. ``~/.config/nix/nix.conf``).
+
+**Pure build with Nix:**
 
 ```shell
-nix-channel --add https://nixbld.m-labs.hk/channel/custom/artiq/fast-beta/artiq-fast
-nix-channel --update
+nix build .#zc706-nist_clock-jtag  # or zc706-nist_qc2-jtag or zc706-nist_clock-sd or etc
 ```
 
-Note: if you are using Nix channels the first time, you need to be aware of this bug: https://github.com/NixOS/nix/issues/3831
+Run ``nix flake show`` to see all valid build targets. Targets suffixed with ``-jtag`` produce separate firmware and gateware files, intended for use in booting via JTAG server/Ethernet, e.g. ``./remote_run.sh -i`` with a remote JTAG server. Targets suffixed with ``-sd`` will produce ``boot.bin`` file suitable for SD card boot. ``-firmware`` and ``-gateware`` respectively build firmware and gateware only.
 
-Pure build with Nix and execution on a remote JTAG server:
+The Kasli-SoC target requires a system description file as input. See ARTIQ manual for exact instructions or use incremental build.
+
+**Impure incremental build:**
+
+For boards with fixed variants, i.e. ZC706, etc. :
 
 ```shell
-nix-build -A zc706-simple-jtag  # or zc706-nist_qc2-jtag or zc706-nist_clock-jtag
-./remote_run.sh
-```
-
-Impure incremental build and execution on a remote JTAG server:
-
-```shell
-nix-shell
+nix develop
 cd src
-gateware/zc706.py -g ../build/gateware  # build gateware
-make                                    # build firmware
-cd ..
-./remote_run.sh -i
+gateware/<board>.py -g ../build/gateware -V <variant> # gateware
+make GWARGS="-V <variant>" <runtime/satman>    # firmware
+```
+
+For boards with system descriptions, i.e. Kasli-SoC, etc. :
+
+```shell
+nix develop
+cd src
+gateware/<board>.py -g ../build/gateware <description.json> # gateware
+make TARGET=<board> GWARGS="path/to/description.json" <runtime/satman> # firmware
+```
+
+``szl.elf`` can be obtained with:
+
+```shell
+nix build git+https://git.m-labs.hk/m-labs/zynq-rs#<board>-szl
+```
+
+To generate ``boot.bin`` use ``mkbootimage``, e.g.:
+
+```shell
+echo "the_ROM_image:
+    {
+        [bootloader]result/szl.elf
+        gateware/top.bit
+        [elf_use_ph]firmware/armv7-none-eabihf/release/<runtime/satman>
+    }
+    EOF" >> boot.bif
+mkbootimage boot.bif boot.bin
 ```
 
 Notes:
 
-- This is developed with Nixpkgs 20.09, and the ``nixbld.m-labs.hk`` binary substituter can also be used here (see the ARTIQ manual for the public key and instructions).
 - The impure build process is also compatible with non-Nix systems.
-- If the board is connected to the local machine, use the ``local_run.sh`` script.
-- To update ``zynq-rs``, update the cargo files as per usual for Rust projects, but also keep ``zynq-rs.nix`` in sync.
+- Firmware type must be either ``runtime`` for DRTIO-less or DRTIO master variants, or ``satman`` for DRTIO satellite.
+- If the board is connected to the local machine by JTAG, use the ``local_run.sh`` script.
+- A known Xilinx hardware bug prevents repeatedly loading the bootloader over JTAG without a POR reset. If booting over JTAG, install a jumper on ``PS_POR_B`` and use the POR reset script [here](https://git.m-labs.hk/M-Labs/zynq-rs/src/branch/master/kasli_soc_por.py).
+
+Pre-Commit Hooks
+----------------
+
+You are strongly recommended to use the provided pre-commit hooks to automatically reformat files and check for non-optimal Rust/C/C++ practices. Run `pre-commit install` to install the hook and `pre-commit` will automatically run `cargo fmt`, `cargo clippy`, and `clang-format` for you.
+
+Several things to note:
+
+- If `cargo fmt`, `cargo clippy`, or `clang-format` returns an error, the pre-commit hook will fail. You should fix all errors before trying to commit again.
+- If `cargo fmt` or `clang-format` reformats some files, the pre-commit hook will also fail. You should review the changes and, if satisfied, try to commit again.
 
 License
 -------
 
-Copyright (C) 2019-2020 M-Labs Limited.
+Copyright (C) 2019-2024 M-Labs Limited.
 
 ARTIQ is free software: you can redistribute it and/or modify
 it under the terms of the GNU Lesser General Public License as published by

default.nix

@@ -1,146 +0,0 @@
-let
-  zynq-rs = (import ./zynq-rs.nix);
-  pkgs = import <nixpkgs> { overlays = [ (import "${zynq-rs}/nix/mozilla-overlay.nix") ]; };
-  rustPlatform = (import "${zynq-rs}/nix/rust-platform.nix" { inherit pkgs; });
-  cargo-xbuild = (import zynq-rs).cargo-xbuild;
-  mkbootimage = import "${zynq-rs}/nix/mkbootimage.nix" { inherit pkgs; };
-  artiqpkgs = import <artiq-fast/default.nix> { inherit pkgs; };
-  vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
-  # FSBL configuration supplied by Vivado 2020.1 for these boards:
-  fsblTargets = ["zc702" "zc706" "zed"];
-  build = { target, variant }: let
-    szl = (import zynq-rs)."${target}-szl";
-    fsbl = import "${zynq-rs}/nix/fsbl.nix" {
-      inherit pkgs;
-      board = target;
-    };
-
-    firmware = rustPlatform.buildRustPackage rec {
-      # note: due to fetchCargoTarball, cargoSha256 depends on package name
-      name = "firmware";
-
-      src = ./src;
-      cargoSha256 = "1d84yknyizbxgsqj478339fxcyvxq9pzdv0ljrwrgmzgfynqmssj";
-
-      nativeBuildInputs = [
-        pkgs.gnumake
-        (pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
-        cargo-xbuild
-        pkgs.llvmPackages_9.llvm
-        pkgs.llvmPackages_9.clang-unwrapped
-      ];
-      buildPhase = ''
-        export XARGO_RUST_SRC="${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library"
-        export CARGO_HOME=$(mktemp -d cargo-home.XXX)
-        make TARGET=${target} VARIANT=${variant}
-      '';
-
-      installPhase = ''
-        mkdir -p $out $out/nix-support
-        cp ../build/runtime.bin $out/runtime.bin
-        cp ../build/firmware/armv7-none-eabihf/release/runtime $out/runtime.elf
-        echo file binary-dist $out/runtime.bin >> $out/nix-support/hydra-build-products
-        echo file binary-dist $out/runtime.elf >> $out/nix-support/hydra-build-products
-      '';
-
-      doCheck = false;
-      dontFixup = true;
-    };
-    gateware = pkgs.runCommand "${target}-${variant}-gateware"
-      {
-        nativeBuildInputs = [ 
-          (pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
-          vivado
-        ];
-      }
-      ''
-        python ${./src/gateware}/${target}.py -g build -V ${variant}
-        mkdir -p $out $out/nix-support
-        cp build/top.bit $out
-        echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
-      '';
-
-    # SZL startup
-    jtag = pkgs.runCommand "${target}-${variant}-jtag" {}
-      ''
-        mkdir $out
-        ln -s ${szl}/szl.elf $out
-        ln -s ${firmware}/runtime.bin $out
-        ln -s ${gateware}/top.bit $out
-      '';
-    sd = pkgs.runCommand "${target}-${variant}-sd"
-      {
-        buildInputs = [ mkbootimage ];
-      }
-      ''
-      # Do not use "long" paths in boot.bif, because embedded developers
-      # can't write software (mkbootimage will segfault).
-      bifdir=`mktemp -d`
-      cd $bifdir
-      ln -s ${szl}/szl.elf szl.elf
-      ln -s ${firmware}/runtime.elf runtime.elf
-      ln -s ${gateware}/top.bit top.bit
-      cat > boot.bif << EOF
-      the_ROM_image:
-      {
-        [bootloader]szl.elf
-        top.bit
-        runtime.elf
-      }
-      EOF
-      mkdir $out $out/nix-support
-      mkbootimage boot.bif $out/boot.bin
-      echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
-      '';
-
-    # FSBL startup
-    fsbl-sd = pkgs.runCommand "${target}-${variant}-fsbl-sd"
-      {
-        buildInputs = [ mkbootimage ];
-      }
-      ''
-      bifdir=`mktemp -d`
-      cd $bifdir
-      ln -s ${fsbl}/fsbl.elf fsbl.elf
-      ln -s ${gateware}/top.bit top.bit
-      ln -s ${firmware}/runtime.elf runtime.elf
-      cat > boot.bif << EOF
-      the_ROM_image:
-      {
-        [bootloader]fsbl.elf
-        top.bit
-        runtime.elf
-      }
-      EOF
-      mkdir $out $out/nix-support
-      mkbootimage boot.bif $out/boot.bin
-      echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
-      '';
-  in {
-    "${target}-${variant}-firmware" = firmware;
-    "${target}-${variant}-gateware" = gateware;
-    "${target}-${variant}-jtag" = jtag;
-    "${target}-${variant}-sd" = sd;
-  } // (
-    if builtins.elem target fsblTargets
-    then {
-      "${target}-${variant}-fsbl-sd" = fsbl-sd;
-    }
-    else {}
-  );
-in
-  (
-    (build { target = "zc706"; variant = "simple"; }) //
-    (build { target = "zc706"; variant = "nist_clock"; }) //
-    (build { target = "zc706"; variant = "nist_qc2"; }) //
-    (build { target = "zc706"; variant = "acpki_simple"; }) //
-    (build { target = "zc706"; variant = "acpki_nist_clock"; }) //
-    (build { target = "zc706"; variant = "acpki_nist_qc2"; }) //
-    (build { target = "coraz7"; variant = "10"; }) //
-    (build { target = "coraz7"; variant = "07s"; }) //
-    (build { target = "coraz7"; variant = "acpki_10"; }) //
-    (build { target = "coraz7"; variant = "acpki_07s"; }) //
-    (build { target = "redpitaya"; variant = "simple"; }) //
-    (build { target = "redpitaya"; variant = "acpki_simple"; }) //
-    { inherit zynq-rs; }
-  )

demo.json

@@ -0,0 +1,63 @@
+{
+    "target": "kasli_soc",
+    "variant": "demo",
+    "hw_rev": "v1.0",
+    "drtio_role": "standalone",
+    "peripherals": [
+        {
+            "type": "coaxpress_sfp"
+        },
+        {
+            "type": "grabber",
+            "ports": [0]
+        },
+        {
+            "type": "dio",
+            "ports": [1],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [2],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [3, 4],
+            "clk_sel": 2
+        },
+        {
+            "type": "zotino",
+            "ports": [5]
+        },
+        {
+            "type": "sampler",
+            "ports": [6, 7]
+        },
+        {
+            "type": "mirny",
+            "ports": [8],
+            "clk_sel": 1,
+            "refclk": 125e6
+        },
+        {
+            "type": "fastino",
+            "ports": [9]
+        },
+        {
+            "type": "dio",
+            "ports": [10],
+            "bank_direction_low": "input",
+            "bank_direction_high": "input"
+        },
+        {
+            "type": "dio",
+            "ports": [11],
+            "bank_direction_low": "output",
+            "bank_direction_high": "input"
+        }
+    ]
+}

examples/device_db.py

@@ -1,87 +0,0 @@
-# For NIST_QC2
-
-device_db = {
-    "core": {
-        "type": "local",
-        "module": "artiq.coredevice.core",
-        "class": "Core",
-        "arguments": {
-            "host": "192.168.1.52",
-            "ref_period": 1e-9,
-            "ref_multiplier": 1,
-            "target": "cortexa9"
-        }
-    },
-    "core_cache": {
-        "type": "local",
-        "module": "artiq.coredevice.cache",
-        "class": "CoreCache"
-    },
-    "core_dma": {
-        "type": "local",
-        "module": "artiq.coredevice.dma",
-        "class": "CoreDMA"
-    },
-
-    "i2c_switch": {
-        "type": "local",
-        "module": "artiq.coredevice.i2c",
-        "class": "PCA9548"
-    },
-
-    # led? are common to all variants
-    "led0": {
-        "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLOut",
-        "arguments": {"channel": 0},
-    },
-    "led1": {
-        "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLOut",
-        "arguments": {"channel": 1},
-    },
-    "led2": {
-        "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLOut",
-        "arguments": {"channel": 2}
-    },
-    "led3": {
-        "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLOut",
-        "arguments": {"channel": 3}
-    },
-}
-
-# TTLs on QC2 backplane
-for i in range(40):
-    device_db["ttl" + str(i)] = {
-        "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLInOut",
-        "arguments": {"channel": 4+i}
-    }
-
-device_db["ad9914dds0"] = {
-    "type": "local",
-    "module": "artiq.coredevice.ad9914",
-    "class": "AD9914",
-    "arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 0},
-}
-device_db["ad9914dds1"] = {
-    "type": "local",
-    "module": "artiq.coredevice.ad9914",
-    "class": "AD9914",
-    "arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1},
-}
-
-# for ARTIQ test suite
-device_db.update(
-    loop_out="ttl0",
-    loop_in="ttl1",
-    ttl_out="ttl2",
-    ttl_out_serdes="ttl2",
-)

examples/device_db.py

@@ -0,0 +1 @@
+device_db_zc706.py

examples/device_db_ebaz4205.py

@@ -0,0 +1,78 @@
+core_addr = "192.168.1.57"
+
+device_db = {
+    "core": {
+        "type": "local",
+        "module": "artiq.coredevice.core",
+        "class": "Core",
+        "arguments": {
+            "host": core_addr,
+            "ref_period": 1e-9,
+            "target": "cortexa9",
+        },
+    },
+    "core_log": {
+        "type": "controller",
+        "host": "::1",
+        "port": 1068,
+        "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr,
+    },
+    "core_moninj": {
+        "type": "controller",
+        "host": "::1",
+        "port_proxy": 1383,
+        "port": 1384,
+        "command": "aqctl_moninj_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} "
+        + core_addr,
+    },
+    "core_analyzer": {
+        "type": "controller",
+        "host": "::1",
+        "port_proxy": 1385,
+        "port": 1386,
+        "command": "aqctl_coreanalyzer_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} "
+        + core_addr,
+    },
+    "core_cache": {
+        "type": "local",
+        "module": "artiq.coredevice.cache",
+        "class": "CoreCache",
+    },
+    "core_dma": {"type": "local", "module": "artiq.coredevice.dma", "class": "CoreDMA"},
+    "led0": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 0},
+    },
+    "led1": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 1},
+    },
+}
+
+# TTLs starting at RTIO channel 2, ending at RTIO channel 15
+for i in range(2, 16):
+    device_db["ttl" + str(i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": i},
+    }
+
+device_db.update(
+    spi0={
+        "type": "local",
+        "module": "artiq.coredevice.spi2",
+        "class": "SPIMaster",
+        "arguments": {"channel": 16},
+    },
+    dds0={
+        "type": "local",
+        "module": "artiq.coredevice.ad9834",
+        "class": "AD9834",
+        "arguments": {"spi_device": "spi0"},
+    },
+)

examples/device_db_zc706.py

@@ -0,0 +1,86 @@
+# For NIST_QC2
+
+import os
+
+device_db = {
+    "core": {
+        "type": "local",
+        "module": "artiq.coredevice.core",
+        "class": "Core",
+        "arguments": {
+            "host": "192.168.1.52",
+            "ref_period": 1e-9,
+            "ref_multiplier": 8,
+            "target": "cortexa9"
+        }
+    },
+    "core_cache": {
+        "type": "local",
+        "module": "artiq.coredevice.cache",
+        "class": "CoreCache"
+    },
+    "core_dma": {
+        "type": "local",
+        "module": "artiq.coredevice.dma",
+        "class": "CoreDMA"
+    },
+
+    "i2c_switch": {
+        "type": "local",
+        "module": "artiq.coredevice.i2c",
+        "class": "PCA9548"
+    },
+
+    "led0": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 41},
+    },
+}
+
+# TTLs on QC2 backplane
+for i in range(40):
+    device_db["ttl" + str(i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": i}
+    }
+
+device_db["ad9914dds0"] = {
+    "type": "local",
+    "module": "artiq.coredevice.ad9914",
+    "class": "AD9914",
+    "arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 0},
+}
+device_db["ad9914dds1"] = {
+    "type": "local",
+    "module": "artiq.coredevice.ad9914",
+    "class": "AD9914",
+    "arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1},
+}
+
+for i in range(4):
+    device_db["ttl"+str(i)+"_counter"] = {
+        "type": "local",
+        "module": "artiq.coredevice.edge_counter",
+        "class": "EdgeCounter",
+        "arguments": {"channel": 52+i}
+    }
+
+# for ARTIQ test suite
+device_db.update(
+    loop_out="ttl0",
+    loop_in="ttl1",
+    ttl_out="ttl2",
+    ttl_out_serdes="ttl2",
+)
+
+if os.environ.get("ENABLE_ACPKI"):
+    device_db["core_batch"] = {
+        "type": "local",
+        "module": "artiq.coredevice.rtio",
+        "class": "RTIOBatch"
+     }
+

flake.lock

@@ -0,0 +1,373 @@
+{
+  "nodes": {
+    "artiq": {
+      "inputs": {
+        "artiq-comtools": "artiq-comtools",
+        "naersk": "naersk",
+        "nixpkgs": "nixpkgs",
+        "rust-overlay": "rust-overlay",
+        "sipyco": "sipyco",
+        "src-migen": "src-migen",
+        "src-misoc": "src-misoc",
+        "src-pythonparser": "src-pythonparser"
+      },
+      "locked": {
+        "lastModified": 1770708569,
+        "narHash": "sha256-Q/qir1PtGhinxNzkm/SzySwtLK0nsc06xn6BBPMuKlw=",
+        "ref": "refs/heads/master",
+        "rev": "80d453eb23c5db45e02b7a84cf9b07ae8bf9bcfd",
+        "revCount": 9621,
+        "type": "git",
+        "url": "https://git.m-labs.hk/m-labs/artiq"
+      },
+      "original": {
+        "type": "git",
+        "url": "https://git.m-labs.hk/m-labs/artiq"
+      }
+    },
+    "artiq-comtools": {
+      "inputs": {
+        "flake-utils": "flake-utils",
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ],
+        "sipyco": [
+          "artiq",
+          "sipyco"
+        ]
+      },
+      "locked": {
+        "lastModified": 1767353405,
+        "narHash": "sha256-KGQqMMN+xavRYEPsBHnNptLvMGxaPzVqHJnYiOEo57c=",
+        "ref": "refs/heads/master",
+        "rev": "3da1f80d702b3a01c4b4fba9e5bc832b79097338",
+        "revCount": 44,
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/artiq-comtools.git"
+      },
+      "original": {
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/artiq-comtools.git"
+      }
+    },
+    "fenix": {
+      "inputs": {
+        "nixpkgs": [
+          "artiq",
+          "naersk",
+          "nixpkgs"
+        ],
+        "rust-analyzer-src": "rust-analyzer-src"
+      },
+      "locked": {
+        "lastModified": 1752475459,
+        "narHash": "sha256-z6QEu4ZFuHiqdOPbYss4/Q8B0BFhacR8ts6jO/F/aOU=",
+        "owner": "nix-community",
+        "repo": "fenix",
+        "rev": "bf0d6f70f4c9a9cf8845f992105652173f4b617f",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-community",
+        "repo": "fenix",
+        "type": "github"
+      }
+    },
+    "fenix_2": {
+      "inputs": {
+        "nixpkgs": [
+          "zynq-rs",
+          "naersk",
+          "nixpkgs"
+        ],
+        "rust-analyzer-src": "rust-analyzer-src_2"
+      },
+      "locked": {
+        "lastModified": 1752475459,
+        "narHash": "sha256-z6QEu4ZFuHiqdOPbYss4/Q8B0BFhacR8ts6jO/F/aOU=",
+        "owner": "nix-community",
+        "repo": "fenix",
+        "rev": "bf0d6f70f4c9a9cf8845f992105652173f4b617f",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-community",
+        "repo": "fenix",
+        "type": "github"
+      }
+    },
+    "flake-utils": {
+      "inputs": {
+        "systems": "systems"
+      },
+      "locked": {
+        "lastModified": 1731533236,
+        "narHash": "sha256-l0KFg5HjrsfsO/JpG+r7fRrqm12kzFHyUHqHCVpMMbI=",
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "rev": "11707dc2f618dd54ca8739b309ec4fc024de578b",
+        "type": "github"
+      },
+      "original": {
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "type": "github"
+      }
+    },
+    "naersk": {
+      "inputs": {
+        "fenix": "fenix",
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1768908532,
+        "narHash": "sha256-HIdLXEFaUVE8FiaCPJbCfBMsnF+mVtDub8Jwj2BD+mk=",
+        "owner": "nix-community",
+        "repo": "naersk",
+        "rev": "8d97452673640eb7fabe428e8b6a425bc355008b",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-community",
+        "repo": "naersk",
+        "type": "github"
+      }
+    },
+    "naersk_2": {
+      "inputs": {
+        "fenix": "fenix_2",
+        "nixpkgs": [
+          "zynq-rs",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1769799857,
+        "narHash": "sha256-88IFXZ7Sa1vxbz5pty0Io5qEaMQMMUPMonLa3Ls/ss4=",
+        "owner": "nix-community",
+        "repo": "naersk",
+        "rev": "9d4ed44d8b8cecdceb1d6fd76e74123d90ae6339",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-community",
+        "repo": "naersk",
+        "type": "github"
+      }
+    },
+    "nixpkgs": {
+      "locked": {
+        "lastModified": 1768940263,
+        "narHash": "sha256-sJERJIYTKPFXkoz/gBaBtRKke82h4DkX3BBSsKbfbvI=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "3ceaaa8bc963ced4d830e06ea2d0863b6490ff03",
+        "type": "github"
+      },
+      "original": {
+        "owner": "NixOS",
+        "ref": "nixos-25.11",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "root": {
+      "inputs": {
+        "artiq": "artiq",
+        "zynq-rs": "zynq-rs"
+      }
+    },
+    "rust-analyzer-src": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1752428706,
+        "narHash": "sha256-EJcdxw3aXfP8Ex1Nm3s0awyH9egQvB2Gu+QEnJn2Sfg=",
+        "owner": "rust-lang",
+        "repo": "rust-analyzer",
+        "rev": "591e3b7624be97e4443ea7b5542c191311aa141d",
+        "type": "github"
+      },
+      "original": {
+        "owner": "rust-lang",
+        "ref": "nightly",
+        "repo": "rust-analyzer",
+        "type": "github"
+      }
+    },
+    "rust-analyzer-src_2": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1752428706,
+        "narHash": "sha256-EJcdxw3aXfP8Ex1Nm3s0awyH9egQvB2Gu+QEnJn2Sfg=",
+        "owner": "rust-lang",
+        "repo": "rust-analyzer",
+        "rev": "591e3b7624be97e4443ea7b5542c191311aa141d",
+        "type": "github"
+      },
+      "original": {
+        "owner": "rust-lang",
+        "ref": "nightly",
+        "repo": "rust-analyzer",
+        "type": "github"
+      }
+    },
+    "rust-overlay": {
+      "inputs": {
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1719454714,
+        "narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
+        "owner": "oxalica",
+        "repo": "rust-overlay",
+        "rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "oxalica",
+        "ref": "snapshot/2024-08-01",
+        "repo": "rust-overlay",
+        "type": "github"
+      }
+    },
+    "rust-overlay_2": {
+      "inputs": {
+        "nixpkgs": [
+          "zynq-rs",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1771038269,
+        "narHash": "sha256-TygYZ7JhnJbRoWOk7d5HaA/GhEVCvtRruN7TqaN9s/c=",
+        "owner": "oxalica",
+        "repo": "rust-overlay",
+        "rev": "d7a86c8a4df49002446737603a3e0d7ef91a9637",
+        "type": "github"
+      },
+      "original": {
+        "owner": "oxalica",
+        "repo": "rust-overlay",
+        "type": "github"
+      }
+    },
+    "sipyco": {
+      "inputs": {
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1767320872,
+        "narHash": "sha256-0lUkzOxOnjk3vQdsL9Yt3KLctYBTZgIRd8RvcITbqO0=",
+        "ref": "refs/heads/master",
+        "rev": "ce454bb64257b1bcef3703f258aaf7fa4ee0c275",
+        "revCount": 154,
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/sipyco.git"
+      },
+      "original": {
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/sipyco.git"
+      }
+    },
+    "src-migen": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1768997857,
+        "narHash": "sha256-bdKQUQ3XLc4fV5sYBfKMuHuOS7nlF0ZU7rjWIKDzFzA=",
+        "ref": "refs/heads/master",
+        "rev": "44e5627d367c528b3ce5e686b6f305a9dfc56f2a",
+        "revCount": 2076,
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/migen.git"
+      },
+      "original": {
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/migen.git"
+      }
+    },
+    "src-misoc": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1765867404,
+        "narHash": "sha256-YPYUHVIryXDp4W2hUtHUtBbRKIrbhInWImT0NKaacSY=",
+        "ref": "refs/heads/master",
+        "rev": "7ab412de11f6533cd68cd818924da5c28a484ccd",
+        "revCount": 2509,
+        "submodules": true,
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/misoc.git"
+      },
+      "original": {
+        "submodules": true,
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/misoc.git"
+      }
+    },
+    "src-pythonparser": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1767427016,
+        "narHash": "sha256-E57okn+3gwvtXnF/qF/jypNYqijCLUYOEYLF9ZCzHpE=",
+        "ref": "refs/heads/master",
+        "rev": "a2ace427c84ee5b1e9bd9dbc9b9337e50fc54077",
+        "revCount": 152,
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/pythonparser.git"
+      },
+      "original": {
+        "type": "git",
+        "url": "https://git.m-labs.hk/M-Labs/pythonparser.git"
+      }
+    },
+    "systems": {
+      "locked": {
+        "lastModified": 1681028828,
+        "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
+        "owner": "nix-systems",
+        "repo": "default",
+        "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-systems",
+        "repo": "default",
+        "type": "github"
+      }
+    },
+    "zynq-rs": {
+      "inputs": {
+        "naersk": "naersk_2",
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ],
+        "rust-overlay": "rust-overlay_2"
+      },
+      "locked": {
+        "lastModified": 1771064140,
+        "narHash": "sha256-udr/yfbyupzRr2HAYlqE/XMZ5lbPX3arYESrJ3hqKrc=",
+        "ref": "refs/heads/master",
+        "rev": "6e4e0548a2b98a6acdec8bb306caa08af8f41c2e",
+        "revCount": 742,
+        "type": "git",
+        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
+      },
+      "original": {
+        "type": "git",
+        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
+      }
+    }
+  },
+  "root": "root",
+  "version": 7
+}

flake.nix

@@ -0,0 +1,549 @@
+{
+  description = "ARTIQ port to the Zynq-7000 platform";
+
+  inputs.artiq.url = git+https://git.m-labs.hk/m-labs/artiq;
+  inputs.zynq-rs.url = git+https://git.m-labs.hk/m-labs/zynq-rs;
+  inputs.zynq-rs.inputs.nixpkgs.follows = "artiq/nixpkgs";
+
+  outputs = {
+    self,
+    zynq-rs,
+    artiq,
+  }: let
+    pkgs = import artiq.inputs.nixpkgs {
+      system = "x86_64-linux";
+      overlays = [(import zynq-rs.inputs.rust-overlay)];
+    };
+    zynqpkgs = zynq-rs.packages.x86_64-linux;
+    artiqpkgs = artiq.packages.x86_64-linux;
+    zynqRev = self.sourceInfo.rev or "unknown";
+
+    rust = zynq-rs.rust;
+    naerskLib = zynq-rs.naerskLib;
+
+    fastnumbers = pkgs.python3Packages.buildPythonPackage rec {
+      pname = "fastnumbers";
+      version = "5.1.0";
+
+      src = pkgs.python3Packages.fetchPypi {
+        inherit pname version;
+        sha256 = "sha256-4JLTP4uVwxcaL7NOV57+DFSwKQ3X+W/6onYkN2AdkKc=";
+      };
+      pyproject = true;
+      build-system = [pkgs.python3Packages.setuptools];
+    };
+
+    artiq-netboot = pkgs.python3Packages.buildPythonPackage rec {
+      pname = "artiq-netboot";
+      version = "unstable-2020-10-15";
+
+      src = pkgs.fetchgit {
+        url = "https://git.m-labs.hk/m-labs/artiq-netboot.git";
+        rev = "04f69eb07df73abe4b89fde2c24084f7664f2104";
+        sha256 = "0ql4fr8m8gpb2yql8aqsdqsssxb8zqd6l65kl1f6s9845zy7shs9";
+      };
+      pyproject = true;
+      build-system = [pkgs.python3Packages.setuptools];
+    };
+
+    ramda = pkgs.python3Packages.buildPythonPackage {
+      pname = "ramda";
+      version = "unstable-2020-04-11";
+
+      src = pkgs.fetchFromGitHub {
+        owner = "peteut";
+        repo = "ramda.py";
+        rev = "d315a9717ebd639366bf3fe26bad9e3d08ec3c49";
+        sha256 = "sha256-bmSt/IHDnULsZjsC6edELnNH7LoJSVF4L4XhwBAXRkY=";
+      };
+      pyproject = true;
+      build-system = [pkgs.python3Packages.setuptools];
+
+      nativeBuildInputs = with pkgs.python3Packages; [pbr];
+      propagatedBuildInputs = with pkgs.python3Packages; [fastnumbers];
+
+      checkInputs = with pkgs.python3Packages; [pytest];
+      checkPhase = "pytest";
+      doCheck = false;
+
+      preBuild = ''
+        export PBR_VERSION=0.5.5
+      '';
+    };
+
+    migen-axi = pkgs.python3Packages.buildPythonPackage {
+      pname = "migen-axi";
+      version = "unstable-2023-01-06";
+
+      src = pkgs.fetchFromGitHub {
+        owner = "peteut";
+        repo = "migen-axi";
+        rev = "98649a92ed7d4e43f75231e6ef9753e1212fab41";
+        sha256 = "sha256-0kEHK+l6gZW750tq89fHRxIh3Gnj5EP2GZX/neWaWzU=";
+      };
+      pyproject = true;
+      build-system = [pkgs.python3Packages.setuptools];
+
+      propagatedBuildInputs = with pkgs.python3Packages; [setuptools click numpy toolz jinja2 ramda artiqpkgs.migen artiqpkgs.misoc];
+
+      checkInputs = with pkgs.python3Packages; [pytestCheckHook pytest-timeout];
+
+      # migen/misoc version checks are broken with pyproject for some reason
+      postPatch = ''
+        sed -i "1,4d" pyproject.toml
+        substituteInPlace pyproject.toml \
+          --replace '"migen@git+https://github.com/m-labs/migen",' ""
+        substituteInPlace pyproject.toml \
+          --replace '"misoc@git+https://github.com/m-labs/misoc.git",' ""
+        # pytest-flake8 is broken with recent flake8. Re-enable after fix.
+        substituteInPlace setup.cfg --replace '--flake8' ""
+      '';
+    };
+    binutils = {
+      platform,
+      target,
+      zlib,
+    }:
+      pkgs.stdenv.mkDerivation rec {
+        basename = "binutils";
+        version = "2.30";
+        name = "${basename}-${platform}-${version}";
+        src = pkgs.fetchurl {
+          url = "https://ftp.gnu.org/gnu/binutils/binutils-${version}.tar.bz2";
+          sha256 = "028cklfqaab24glva1ks2aqa1zxa6w6xmc8q34zs1sb7h22dxspg";
+        };
+        configureFlags = ["--enable-shared" "--enable-deterministic-archives" "--target=${target}"];
+        outputs = ["out" "info" "man"];
+        depsBuildBuild = [pkgs.buildPackages.stdenv.cc];
+        buildInputs = [zlib];
+        enableParallelBuilding = true;
+      };
+    binutils-arm = pkgs.callPackage binutils {
+      platform = "arm";
+      target = "armv7-unknown-linux-gnueabihf";
+    };
+
+    # FSBL configuration supplied by Vivado 2020.1 for these boards:
+    fsblTargets = ["zc702" "zc706" "zed"];
+    sat_variants = [
+      # kasli-soc satellite variants
+      "satellite"
+      # zc706 satellite variants
+      "nist_clock_satellite"
+      "nist_qc2_satellite"
+      "acpki_nist_clock_satellite"
+      "acpki_nist_qc2_satellite"
+      "nist_clock_satellite_100mhz"
+      "nist_qc2_satellite_100mhz"
+      "acpki_nist_clock_satellite_100mhz"
+      "acpki_nist_qc2_satellite_100mhz"
+    ];
+    board-package-set = {
+      target,
+      variant,
+      json ? null,
+    }: let
+      szl = zynqpkgs."${target}-szl";
+      fsbl = zynqpkgs."${target}-fsbl";
+      fwtype =
+        if builtins.elem variant sat_variants
+        then "satman"
+        else "runtime";
+
+      firmware = naerskLib.buildPackage rec {
+        name = "firmware";
+        src = ./src;
+        additionalCargoLock = "${rust}/lib/rustlib/src/rust/library/Cargo.lock";
+        singleStep = true;
+
+        nativeBuildInputs = [
+          pkgs.gnumake
+          (pkgs.python3.withPackages (ps: [artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq-build]))
+          pkgs.llvmPackages_20.llvm
+          pkgs.llvmPackages_20.clang-unwrapped
+        ];
+
+        overrideMain = _: {
+          buildPhase = ''
+            export ZYNQ_REV=${zynqRev}
+            export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_20.clang-unwrapped.lib}/lib/clang/20/include"
+            export ZYNQ_RS=${zynq-rs}
+            make TARGET=${target} GWARGS="${
+              if json == null
+              then "-V ${variant}"
+              else json
+            }" ${fwtype}
+          '';
+
+          installPhase = ''
+            mkdir -p $out $out/nix-support
+            cp ../build/${fwtype}.bin $out/${fwtype}.bin
+            cp ../build/firmware/armv7-none-eabihf/release/${fwtype} $out/${fwtype}.elf
+            echo file binary-dist $out/${fwtype}.bin >> $out/nix-support/hydra-build-products
+            echo file binary-dist $out/${fwtype}.elf >> $out/nix-support/hydra-build-products
+          '';
+
+          doCheck = false;
+          dontFixup = true;
+        };
+      };
+      gateware =
+        pkgs.runCommand "${target}-${variant}-gateware"
+        {
+          nativeBuildInputs = [
+            (pkgs.python3.withPackages (ps: [artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq-build]))
+            artiqpkgs.vivado
+          ];
+        }
+        ''
+          export ZYNQ_REV=${zynqRev}
+          python ${./src/gateware}/${target}.py -g build ${
+            if json == null
+            then "-V ${variant}"
+            else json
+          }
+          mkdir -p $out $out/nix-support
+          cp build/top.bit $out
+          echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
+        '';
+
+      # SZL startup
+      jtag =
+        pkgs.runCommand "${target}-${variant}-jtag" {}
+        ''
+          mkdir $out
+          ln -s ${szl}/szl.elf $out
+          ln -s ${firmware}/${fwtype}.bin $out
+          ln -s ${gateware}/top.bit $out
+        '';
+      sd =
+        pkgs.runCommand "${target}-${variant}-sd"
+        {
+          buildInputs = [zynqpkgs.mkbootimage];
+        }
+        ''
+          # Do not use "long" paths in boot.bif, because embedded developers
+          # can't write software (mkbootimage will segfault).
+          bifdir=`mktemp -d`
+          cd $bifdir
+          ln -s ${szl}/szl.elf szl.elf
+          ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
+          ln -s ${gateware}/top.bit top.bit
+          cat > boot.bif << EOF
+          the_ROM_image:
+          {
+            [bootloader]szl.elf
+            top.bit
+            [elf_use_ph]${fwtype}.elf
+          }
+          EOF
+          mkdir $out $out/nix-support
+          mkbootimage boot.bif $out/boot.bin
+          echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
+        '';
+
+      # FSBL startup
+      fsbl-sd =
+        pkgs.runCommand "${target}-${variant}-fsbl-sd"
+        {
+          buildInputs = [zynqpkgs.mkbootimage];
+        }
+        ''
+          bifdir=`mktemp -d`
+          cd $bifdir
+          ln -s ${fsbl}/fsbl.elf fsbl.elf
+          ln -s ${gateware}/top.bit top.bit
+          ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
+          cat > boot.bif << EOF
+          the_ROM_image:
+          {
+            [bootloader]fsbl.elf
+            top.bit
+            ${fwtype}.elf
+          }
+          EOF
+          mkdir $out $out/nix-support
+          mkbootimage boot.bif $out/boot.bin
+          echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
+        '';
+    in
+      {
+        "${target}-${variant}-firmware" = firmware;
+        "${target}-${variant}-gateware" = gateware;
+        "${target}-${variant}-jtag" = jtag;
+        "${target}-${variant}-sd" = sd;
+      }
+      // (
+        if builtins.elem target fsblTargets
+        then {
+          "${target}-${variant}-fsbl-sd" = fsbl-sd;
+        }
+        else {}
+      );
+
+    gateware-sim = pkgs.stdenv.mkDerivation {
+      name = "gateware-sim";
+
+      nativeBuildInputs = [
+        (pkgs.python3.withPackages (ps: [artiqpkgs.migen migen-axi artiqpkgs.artiq-build]))
+      ];
+
+      phases = ["buildPhase"];
+
+      buildPhase = ''
+        python -m unittest discover ${self}/src/gateware -v
+        touch $out
+      '';
+    };
+
+    fmt-check = pkgs.stdenvNoCC.mkDerivation {
+      name = "fmt-check";
+
+      src = ./src;
+
+      nativeBuildInputs = [rust pkgs.gnumake];
+
+      phases = ["unpackPhase" "buildPhase"];
+
+      buildPhase = ''
+        export ZYNQ_RS=${zynq-rs}
+        make manifests
+        cargo fmt -- --check
+        touch $out
+      '';
+    };
+
+    # for hitl-tests
+    zc706-nist_qc2 = board-package-set { 
+      target = "zc706"; 
+      variant = "nist_qc2"; 
+    };
+    zc706-acpki_nist_qc2 = board-package-set {
+      target = "zc706"; 
+      variant = "acpki_nist_qc2"; 
+    };
+    make-zc706-hitl-tests = { name, board-package, setup-commands ? ""}: pkgs.stdenv.mkDerivation {
+      name = "zc706-hitl-tests-${name}";
+
+      __networked = true; # compatibility with old patched Nix
+      # breaks hydra, https://github.com/NixOS/hydra/issues/1216
+      #__impure = true;     # Nix 2.8+
+
+      buildInputs = [
+        pkgs.netcat
+        pkgs.openssh
+        pkgs.rsync
+        artiqpkgs.artiq
+        artiq-netboot
+        zynqpkgs.zc706-szl
+      ];
+      phases = ["buildPhase"];
+
+      buildPhase = ''
+        ${setup-commands}
+      
+        export NIX_SSHOPTS="-F /dev/null -o StrictHostKeyChecking=no -o UserKnownHostsFile=/dev/null -o LogLevel=ERROR -i /opt/hydra_id_ed25519"
+        LOCKCTL=$(mktemp -d)
+        mkfifo $LOCKCTL/lockctl
+
+        cat $LOCKCTL/lockctl | ${pkgs.openssh}/bin/ssh \
+        $NIX_SSHOPTS \
+        rpi-4 \
+        'mkdir -p /tmp/board_lock && flock /tmp/board_lock/zc706-1 -c "echo Ok; cat"' \
+        | (
+          # End remote flock via FIFO
+          atexit_unlock() {
+            echo > $LOCKCTL/lockctl
+          }
+          trap atexit_unlock EXIT
+
+          # Read "Ok" line when remote successfully locked
+          read LOCK_OK
+
+          echo Power cycling board...
+          (echo b; sleep 5; echo B; sleep 5) | nc -N -w6 192.168.1.31 3131
+          echo Power cycle done.
+
+          export USER=hydra
+          export OPENOCD_ZYNQ=${zynq-rs}/openocd
+          export SZL=${zynqpkgs.szl}
+          bash ${self}/remote_run.sh -h rpi-4 -o "$NIX_SSHOPTS" -d ${board-package}
+
+          echo Waiting for the firmware to boot...
+          sleep 15
+
+          echo Running test kernel...
+          artiq_run --device-db ${self}/examples/device_db.py ${self}/examples/mandelbrot.py
+
+          echo Running ARTIQ unit tests...
+          export ARTIQ_ROOT=${self}/examples
+          export ARTIQ_LOW_LATENCY=1
+          python -m unittest discover artiq.test.coredevice -v
+
+          touch $out
+
+          echo Completed
+
+          (echo b; sleep 5) | nc -N -w6 192.168.1.31 3131
+          echo Board powered off
+        )
+      '';
+    };
+    zc706-hitl-tests = make-zc706-hitl-tests {
+      name = "nist_qc2";
+      board-package = zc706-nist_qc2.zc706-nist_qc2-jtag;
+    };
+    zc706-acpki-hitl-tests = make-zc706-hitl-tests { 
+      name = "acpki_nist_qc2";
+      board-package = zc706-acpki_nist_qc2.zc706-acpki_nist_qc2-jtag;
+      setup-commands = "export ENABLE_ACPKI=1";
+    };
+
+  in rec {
+    packages.x86_64-linux =
+      {
+        inherit fastnumbers artiq-netboot ramda migen-axi binutils-arm;
+      }
+      // (board-package-set {
+        target = "zc706";
+        variant = "cxp_4r_fmc";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_clock";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_clock_master";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_clock_master_100mhz";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_clock_satellite";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_clock_satellite_100mhz";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_qc2";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_qc2_master";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_qc2_master_100mhz";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_qc2_satellite";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "nist_qc2_satellite_100mhz";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_clock";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_clock_master";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_clock_master_100mhz";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_clock_satellite";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_clock_satellite_100mhz";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_qc2";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_qc2_master";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_qc2_master_100mhz";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_qc2_satellite";
+      })
+      // (board-package-set {
+        target = "zc706";
+        variant = "acpki_nist_qc2_satellite_100mhz";
+      })
+      // (board-package-set {
+        target = "kasli_soc";
+        variant = "demo";
+        json = ./demo.json;
+      })
+      // (board-package-set {
+        target = "kasli_soc";
+        variant = "master";
+        json = ./kasli-soc-master.json;
+      })
+      // (board-package-set {
+        target = "kasli_soc";
+        variant = "satellite";
+        json = ./kasli-soc-satellite.json;
+      })
+      // (board-package-set {
+        target = "ebaz4205";
+        variant = "base";
+      });
+
+    hydraJobs =
+      packages.x86_64-linux
+      // {
+        inherit zc706-hitl-tests;
+        inherit zc706-acpki-hitl-tests;
+        inherit gateware-sim;
+        inherit fmt-check;
+      };
+
+    formatter.x86_64-linux = pkgs.alejandra;
+
+    devShell.x86_64-linux = pkgs.mkShell {
+      name = "artiq-zynq-dev-shell";
+      buildInputs = with pkgs; [
+        rust
+        llvmPackages_20.llvm
+        llvmPackages_20.clang-unwrapped
+        gnumake
+        cacert
+        zynqpkgs.mkbootimage
+        openocd
+        openssh
+        rsync
+        (python3.withPackages (ps: (with artiqpkgs; [migen migen-axi misoc artiq artiq-netboot ps.jsonschema ps.pyftdi])))
+        artiqpkgs.artiq
+        artiqpkgs.vivado
+        binutils-arm
+        pre-commit
+      ];
+      ZYNQ_REV = "${zynqRev}";
+      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_20.clang-unwrapped.lib}/lib/clang/20/include";
+      ZYNQ_RS = "${zynq-rs}";
+      OPENOCD_ZYNQ = "${zynq-rs}/openocd";
+      SZL = "${zynqpkgs.szl}";
+    };
+
+    makeArtiqZynqPackage = board-package-set;
+  };
+}

kasli-soc-master.json

@@ -0,0 +1,63 @@
+{
+    "target": "kasli_soc",
+    "variant": "master",
+    "hw_rev": "v1.0",
+    "drtio_role": "master",
+    "peripherals": [
+        {
+            "type": "coaxpress_sfp"
+        },
+        {
+            "type": "grabber",
+            "ports": [0]
+        },
+        {
+            "type": "dio",
+            "ports": [1],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [2],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [3, 4],
+            "clk_sel": 2
+        },
+        {
+            "type": "zotino",
+            "ports": [5]
+        },
+        {
+            "type": "sampler",
+            "ports": [6, 7]
+        },
+        {
+            "type": "mirny",
+            "ports": [8],
+            "clk_sel": 1,
+            "refclk": 125e6
+        },
+        {
+            "type": "fastino",
+            "ports": [9]
+        },
+        {
+            "type": "dio",
+            "ports": [10],
+            "bank_direction_low": "input",
+            "bank_direction_high": "input"
+        },
+        {
+            "type": "dio",
+            "ports": [11],
+            "bank_direction_low": "output",
+            "bank_direction_high": "input"
+        }
+    ]
+}

kasli-soc-satellite.json

@@ -0,0 +1,63 @@
+{
+    "target": "kasli_soc",
+    "variant": "satellite",
+    "hw_rev": "v1.0",
+    "drtio_role": "satellite",
+    "peripherals": [
+        {
+            "type": "coaxpress_sfp"
+        },
+        {
+            "type": "grabber",
+            "ports": [0]
+        },
+        {
+            "type": "dio",
+            "ports": [1],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [2],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [3, 4],
+            "clk_sel": 2
+        },
+        {
+            "type": "zotino",
+            "ports": [5]
+        },
+        {
+            "type": "sampler",
+            "ports": [6, 7]
+        },
+        {
+            "type": "mirny",
+            "ports": [8],
+            "clk_sel": 1,
+            "refclk": 125e6
+        },
+        {
+            "type": "fastino",
+            "ports": [9]
+        },
+        {
+            "type": "dio",
+            "ports": [10],
+            "bank_direction_low": "input",
+            "bank_direction_high": "input"
+        },
+        {
+            "type": "dio",
+            "ports": [11],
+            "bank_direction_low": "output",
+            "bank_direction_high": "input"
+        }
+    ]
+}

local_run.sh

@@ -13,9 +13,10 @@ fi
 
 impure=0
 load_bitstream=1
-board_host="192.168.1.52"
+board_type="kasli_soc"
+fw_type="runtime"
 
-while getopts "ilb:" opt; do
+while getopts "ilb:t:f:" opt; do
     case "$opt" in
     \?) exit 1
         ;;
@@ -25,24 +26,36 @@ while getopts "ilb:" opt; do
         ;;
     b)  board_host=$OPTARG
         ;;
+    t)  board_type=$OPTARG
+        ;;
+    f)  fw_type=$OPTARG
+        ;;
     esac
 done
 
+if [ -z "$board_host" ]; then
+    case $board_type in
+    kasli_soc) board_host="192.168.1.56";;
+    zc706) board_host="192.168.1.52";;
+    *) echo "Unknown board type"; exit 1;;
+    esac
+fi
+
 load_bitstream_cmd=""
 
 build_dir=`pwd`/build
 result_dir=`pwd`/result
 cd $OPENOCD_ZYNQ
-openocd -f zc706.cfg -c "load_image $SZL; resume 0; exit"
+openocd -f $board_type.cfg -c "load_image $SZL/szl-$board_type.elf; resume 0; exit"
 sleep 5
 if [ $impure -eq 1 ]; then
     if [ $load_bitstream -eq 1 ]; then
         load_bitstream_cmd="-g $build_dir/gateware/top.bit"
     fi
-    artiq_netboot $load_bitstream_cmd -f $build_dir/runtime.bin -b $board_host
+    artiq_netboot $load_bitstream_cmd -f $build_dir/$fw_type.bin -b $board_host
 else
     if [ $load_bitstream -eq 1 ]; then
         load_bitstream_cmd="-g $result_dir/top.bit"
     fi
-    artiq_netboot $load_bitstream_cmd -f $result_dir/runtime.bin -b $board_host
-fi
+    artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
+fi

remote_run.sh

@@ -1,5 +1,7 @@
 #!/usr/bin/env bash
 
+# Only ZC706 supported for now.
+
 set -e
 
 if [ -z "$OPENOCD_ZYNQ" ]; then
@@ -11,15 +13,16 @@ if [ -z "$SZL" ]; then
     exit 1
 fi
 
-target_host="rpi-4.m-labs.hk"
+target_host="rpi-4"
 impure=0
 pure_dir="result"
 impure_dir="build"
 sshopts=""
 load_bitstream=1
 board_host="192.168.1.52"
+fw_type="runtime"
 
-while getopts "h:id:o:l" opt; do
+while getopts "h:id:o:lt:" opt; do
     case "$opt" in
     \?) exit 1
         ;;
@@ -36,6 +39,8 @@ while getopts "h:id:o:l" opt; do
         ;;
     b)  board_host=$OPTARG
         ;;
+    t)  fw_type=$OPTARG
+        ;;
     esac
 done
 
@@ -46,17 +51,17 @@ echo "Creating $target_folder..."
 ssh $sshopts $target_host "mkdir -p $target_folder"
 echo "Copying files..."
 rsync -e "ssh $sshopts" -Lc $OPENOCD_ZYNQ/* $target_host:$target_folder
-rsync -e "ssh $sshopts" -Lc $SZL $target_host:$target_folder
+rsync -e "ssh $sshopts" -Lc $SZL/szl-zc706.elf $target_host:$target_folder/szl.elf
 if [ $impure -eq 1 ]; then
     if [ $load_bitstream -eq 1 ]; then
         load_bitstream_cmd="-g build/gateware/top.bit"
     fi
-    firmware="build/runtime.bin"
+    firmware="build/$fw_type.bin"
 else
     if [ $load_bitstream -eq 1 ]; then
         load_bitstream_cmd="-g $pure_dir/top.bit"
     fi
-    firmware="$pure_dir/runtime.bin"    
+    firmware="$pure_dir/$fw_type.bin"    
 fi
 echo "Programming board..."
 ssh $sshopts $target_host "cd $target_folder; openocd -f zc706.cfg -c'load_image szl.elf; resume 0; exit'"

shell.nix

@@ -1,35 +0,0 @@
-let
-  zynq-rs = (import ./zynq-rs.nix);
-  pkgs = import <nixpkgs> { overlays = [ (import "${zynq-rs}/nix/mozilla-overlay.nix") ]; };
-  rustPlatform = (import "${zynq-rs}/nix/rust-platform.nix" { inherit pkgs; });
-  cargo-xbuild = (import zynq-rs).cargo-xbuild;
-  artiq-fast = <artiq-fast>;
-  artiqpkgs = import "${artiq-fast}/default.nix" { inherit pkgs; };
-  vivado = import "${artiq-fast}/vivado.nix" { inherit pkgs; };
-  zc706-szl = (import zynq-rs).zc706-szl;
-in
-  pkgs.stdenv.mkDerivation {
-    name = "artiq-zynq-env";
-    buildInputs = [
-      pkgs.gnumake
-      rustPlatform.rust.rustc
-      rustPlatform.rust.cargo
-      pkgs.llvmPackages_9.llvm
-      pkgs.llvmPackages_9.clang-unwrapped
-      pkgs.cacert
-      cargo-xbuild
-
-      pkgs.openocd
-      pkgs.openssh pkgs.rsync
-
-      (pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq artiq-netboot ])))
-      vivado
-      artiqpkgs.binutils-arm
-
-      (import "${zynq-rs}/nix/mkbootimage.nix" { inherit pkgs; })
-    ];
-
-    XARGO_RUST_SRC = "${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library";
-    OPENOCD_ZYNQ = "${zynq-rs}/openocd";
-    SZL = "${zc706-szl}/szl.elf";
-  }

src/.cargo/config.toml

@@ -1,9 +1,12 @@
 [target.armv7-none-eabihf]
 rustflags = [
   "-C", "link-arg=-Tlink.x",
-  "-C", "target-feature=a9,armv7-a,neon",
+  "-C", "link-arg=--no-check-sections",  # required for overlapping sections
   "-C", "target-cpu=cortex-a9",
 ]
 
 [build]
 target = "armv7-none-eabihf.json"
+
+[unstable]
+build-std = ["core", "alloc", "compiler_builtins"]

src/.clang-format

@@ -0,0 +1,32 @@
+BasedOnStyle: LLVM
+
+Language: Cpp
+Standard: Cpp11
+
+AccessModifierOffset: -1
+AlignEscapedNewlines: Left
+AlwaysBreakAfterReturnType: None
+AlwaysBreakTemplateDeclarations: Yes
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortFunctionsOnASingleLine: Inline
+BinPackParameters: false
+BreakBeforeBinaryOperators: NonAssignment
+BreakBeforeTernaryOperators: true
+BreakConstructorInitializers: AfterColon
+BreakInheritanceList: AfterColon
+ColumnLimit: 120
+ConstructorInitializerAllOnOneLineOrOnePerLine: true
+ContinuationIndentWidth: 4
+DerivePointerAlignment: false
+IndentCaseLabels: true
+IndentPPDirectives: None
+IndentWidth: 4
+MaxEmptyLinesToKeep: 1
+PointerAlignment: Left
+ReflowComments: true
+SortIncludes: false
+SortUsingDeclarations: true
+SpaceAfterTemplateKeyword: false
+SpacesBeforeTrailingComments: 2
+TabWidth: 4
+UseTab: Never

src/.clippy.toml

@@ -0,0 +1 @@
+doc-valid-idents = ["CPython", "NumPy", ".."]

src/.pre-commit-config.yaml

@@ -0,0 +1,32 @@
+# See https://pre-commit.com for more information
+# See https://pre-commit.com/hooks.html for more hooks
+
+default_stages: [commit]
+
+repos:
+  - repo: local
+    hooks:
+      - id: cargo-fmt
+        name: artiq-zynq cargo format
+        entry: nix
+        language: system
+        types: [file, rust]
+        pass_filenames: false
+        description: Runs cargo fmt on the codebase.
+        args: [develop, -c, cargo, fmt, --manifest-path, src/Cargo.toml, --all]
+      - id: cargo-clippy
+        name: artiq-zynq cargo clippy
+        entry: nix
+        language: system
+        types: [file, rust]
+        pass_filenames: false
+        description: Runs cargo clippy on the codebase.
+        args: [develop, -c, cargo, clippy, --manifest-path, src/Cargo.toml, --tests]
+  - repo: https://github.com/pre-commit/mirrors-clang-format
+    rev: v19.1.0
+    hooks:
+      - id: clang-format
+        name: artiq-zynq clang-format
+        description: Runs clang-format on the codebase.
+        files: \.(cpp|h|hpp|c)$
+        args: [-style=file, -fallback-style=none, -assume-filename=src/.clang-format]

src/Cargo.lock

@@ -1,10 +1,27 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
+version = 4
+
+[[package]]
+name = "approx"
+version = "0.5.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "cab112f0a86d568ea0e627cc1d6be74a1e9cd55214684db5561995f6dad897c6"
+dependencies = [
+ "num-traits",
+]
+
+[[package]]
+name = "arrayvec"
+version = "0.7.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "96d30a06541fbafbc7f82ed10c06164cfbd2c401138f6addd8404629c4b16711"
+
 [[package]]
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+version = "1.1.1"
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-checksum = "e5444eec77a9ec2bfe4524139e09195862e981400c4358d3b760cae634e4c4ee"
+checksum = "3b43422f69d8ff38f95f1b2bb76517c91589a924d1559a0e935d7c8ce0274c11"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -13,9 +30,9 @@ dependencies = [
 
 [[package]]
 name = "autocfg"
-version = "1.0.1"
+version = "1.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cdb031dd78e28731d87d56cc8ffef4a8f36ca26c38fe2de700543e627f8a464a"
+checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa"
 
 [[package]]
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@@ -25,21 +42,31 @@ checksum = "dcb6dd1c2376d2e096796e234a70e17e94cc2d5d54ff8ce42b28cef1d0d359a4"
 
 [[package]]
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-version = "1.2.1"
+version = "1.3.2"
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-checksum = "cf1de2fe8c75bc145a2f577add951f8134889b4795d47466a54a5c846d691693"
+checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
+
+[[package]]
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+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b4ae4235e6dac0694637c763029ecea1a2ec9e4e06ec2729bd21ba4d9c863eb7"
+
+[[package]]
+name = "build_zynq"
+version = "0.0.0"
 
 [[package]]
 name = "byteorder"
-version = "1.3.4"
+version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "08c48aae112d48ed9f069b33538ea9e3e90aa263cfa3d1c24309612b1f7472de"
+checksum = "60f0b0d4c0a382d2734228fd12b5a6b5dac185c60e938026fd31b265b94f9bd2"
 
 [[package]]
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-version = "1.0.66"
+version = "1.0.77"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4c0496836a84f8d0495758516b8621a622beb77c0fed418570e50764093ced48"
+checksum = "e9f73505338f7d905b19d18738976aae232eb46b8efc15554ffc56deb5d9ebe4"
 
 [[package]]
 name = "cfg-if"
@@ -48,17 +75,23 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
 
 [[package]]
-name = "compiler_builtins"
-version = "0.1.39"
+name = "cfg-if"
+version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
+checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 
 [[package]]
 name = "core_io"
-version = "0.1.20200410"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
+version = "0.1.0"
+source = "git+https://git.m-labs.hk/M-Labs/rs-core_io.git?rev=e9d3edf027#e9d3edf0272502b0dd6c26e8a4869c2912657615"
+
+[[package]]
+name = "crc"
+version = "1.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d663548de7f5cca343f1e0a48d14dcfb0e9eb4e079ec58883b7251539fa10aeb"
 dependencies = [
- "memchr",
+ "build_const",
 ]
 
 [[package]]
@@ -71,8 +104,8 @@ checksum = "0f8cb7306107e4b10e64994de6d3274bd08996a7c1322a27b86482392f96be0a"
 name = "dwarf"
 version = "0.0.0"
 dependencies = [
- "cfg-if",
- "compiler_builtins",
+ "cfg-if 0.1.10",
+ "cslice",
  "libc",
  "unwind",
 ]
@@ -87,9 +120,9 @@ dependencies = [
 
 [[package]]
 name = "embedded-hal"
-version = "0.2.4"
+version = "0.2.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fa998ce59ec9765d15216393af37a58961ddcefb14c753b4816ba2191d865fcb"
+checksum = "35949884794ad573cf46071e41c9b60efb0cb311e3ca01f7af807af1debc66ff"
 dependencies = [
  "nb 0.1.3",
  "void",
@@ -97,9 +130,8 @@ dependencies = [
 
 [[package]]
 name = "fatfs"
-version = "0.3.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "93079df23039e52059e1f03b4c29fb0c72da2c792aad91bb2236c9fb81d3592e"
+version = "0.3.6"
+source = "git+https://git.m-labs.hk/M-Labs/rust-fatfs.git?rev=4b5e420084#4b5e420084fd1c4a9c105680b687523909b6469c"
 dependencies = [
  "bitflags",
  "byteorder",
@@ -109,9 +141,9 @@ dependencies = [
 
 [[package]]
 name = "futures"
-version = "0.3.8"
+version = "0.3.31"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9b3b0c040a1fe6529d30b3c5944b280c7f0dcb2930d2c3062bca967b602583d0"
+checksum = "65bc07b1a8bc7c85c5f2e110c476c7389b4554ba72af57d8445ea63a576b0876"
 dependencies = [
  "futures-channel",
  "futures-core",
@@ -123,9 +155,9 @@ dependencies = [
 
 [[package]]
 name = "futures-channel"
-version = "0.3.8"
+version = "0.3.31"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4b7109687aa4e177ef6fe84553af6280ef2778bdb7783ba44c9dc3399110fe64"
+checksum = "2dff15bf788c671c1934e366d07e30c1814a8ef514e1af724a602e8a2fbe1b10"
 dependencies = [
  "futures-core",
  "futures-sink",
@@ -133,23 +165,22 @@ dependencies = [
 
 [[package]]
 name = "futures-core"
-version = "0.3.8"
+version = "0.3.31"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "847ce131b72ffb13b6109a221da9ad97a64cbe48feb1028356b836b47b8f1748"
+checksum = "05f29059c0c2090612e8d742178b0580d2dc940c837851ad723096f87af6663e"
 
 [[package]]
 name = "futures-io"
-version = "0.3.8"
+version = "0.3.31"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "611834ce18aaa1bd13c4b374f5d653e1027cf99b6b502584ff8c9a64413b30bb"
+checksum = "9e5c1b78ca4aae1ac06c48a526a655760685149f0d465d21f37abfe57ce075c6"
 
 [[package]]
 name = "futures-macro"
-version = "0.3.8"
+version = "0.3.31"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "77408a692f1f97bcc61dc001d752e00643408fbc922e4d634c655df50d595556"
+checksum = "162ee34ebcb7c64a8abebc059ce0fee27c2262618d7b60ed8faf72fef13c3650"
 dependencies = [
- "proc-macro-hack",
  "proc-macro2",
  "quote",
  "syn",
@@ -157,48 +188,101 @@ dependencies = [
 
 [[package]]
 name = "futures-sink"
-version = "0.3.8"
+version = "0.3.31"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f878195a49cee50e006b02b93cf7e0a95a38ac7b776b4c4d9cc1207cd20fcb3d"
+checksum = "e575fab7d1e0dcb8d0c7bcf9a63ee213816ab51902e6d244a95819acacf1d4f7"
 
 [[package]]
 name = "futures-task"
-version = "0.3.8"
+version = "0.3.31"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7c554eb5bf48b2426c4771ab68c6b14468b6e76cc90996f528c3338d761a4d0d"
+checksum = "f90f7dce0722e95104fcb095585910c0977252f286e354b5e3bd38902cd99988"
 
 [[package]]
 name = "futures-util"
-version = "0.3.8"
+version = "0.3.31"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d304cff4a7b99cfb7986f7d43fbe93d175e72e704a8860787cc95e9ffd85cbd2"
+checksum = "9fa08315bb612088cc391249efdc3bc77536f16c91f6cf495e6fbe85b20a4a81"
 dependencies = [
  "futures-core",
  "futures-macro",
  "futures-sink",
  "futures-task",
- "pin-project",
+ "pin-project-lite",
  "pin-utils",
- "proc-macro-hack",
- "proc-macro-nested",
+]
+
+[[package]]
+name = "io"
+version = "0.0.0"
+dependencies = [
+ "byteorder",
+ "core_io",
+ "libsupport_zynq",
+]
+
+[[package]]
+name = "ksupport"
+version = "0.1.0"
+dependencies = [
+ "build_zynq",
+ "byteorder",
+ "core_io",
+ "cslice",
+ "dwarf",
+ "dyld",
+ "io",
+ "libasync",
+ "libboard_artiq",
+ "libboard_zynq",
+ "libc",
+ "libconfig",
+ "libcortex_a9",
+ "libm",
+ "libregister",
+ "libsupport_zynq",
+ "log",
+ "log_buffer",
+ "nalgebra",
+ "unwind",
+ "vcell",
+ "void",
 ]
 
 [[package]]
 name = "libasync"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
 dependencies = [
  "embedded-hal",
  "libcortex_a9",
  "nb 1.0.0",
- "pin-utils",
  "smoltcp",
 ]
 
+[[package]]
+name = "libboard_artiq"
+version = "0.0.0"
+dependencies = [
+ "build_zynq",
+ "byteorder",
+ "core_io",
+ "crc",
+ "embedded-hal",
+ "io",
+ "libasync",
+ "libboard_zynq",
+ "libconfig",
+ "libcortex_a9",
+ "libregister",
+ "log",
+ "log_buffer",
+ "nb 1.0.0",
+ "void",
+]
+
 [[package]]
 name = "libboard_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
 dependencies = [
  "bit_field",
  "embedded-hal",
@@ -223,18 +307,17 @@ dependencies = [
 [[package]]
 name = "libconfig"
 version = "0.1.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
 dependencies = [
  "core_io",
  "fatfs",
  "libboard_zynq",
+ "libcortex_a9",
  "log",
 ]
 
 [[package]]
 name = "libcortex_a9"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
 dependencies = [
  "bit_field",
  "libregister",
@@ -243,14 +326,13 @@ dependencies = [
 
 [[package]]
 name = "libm"
-version = "0.2.1"
+version = "0.2.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
+checksum = "348108ab3fba42ec82ff6e9564fc4ca0247bdccdc68dd8af9764bbc79c3c8ffb"
 
 [[package]]
 name = "libregister"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
 dependencies = [
  "bit_field",
  "vcell",
@@ -260,10 +342,8 @@ dependencies = [
 [[package]]
 name = "libsupport_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#78d58d17ec7906a6cadd1678576939d20612cf8f"
 dependencies = [
  "cc",
- "compiler_builtins",
  "libboard_zynq",
  "libcortex_a9",
  "libregister",
@@ -273,17 +353,17 @@ dependencies = [
 
 [[package]]
 name = "linked_list_allocator"
-version = "0.8.8"
+version = "0.8.11"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4e6766dff3bf932e0d1c7f1cf27c0a46008f7839f85b015a312c276a4570a399"
+checksum = "822add9edb1860698b79522510da17bef885171f75aa395cff099d770c609c24"
 
 [[package]]
 name = "log"
-version = "0.4.11"
+version = "0.4.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4fabed175da42fed1fa0746b0ea71f412aa9d35e76e95e59b192c64b9dc2bf8b"
+checksum = "51b9bbe6c47d51fc3e1a9b945965946b4c44142ab8792c50835a980d362c2710"
 dependencies = [
- "cfg-if",
+ "cfg-if 1.0.0",
 ]
 
 [[package]]
@@ -299,10 +379,17 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c75de51135344a4f8ed3cfe2720dc27736f7711989703a0b43aadf3753c55577"
 
 [[package]]
-name = "memchr"
-version = "2.3.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0ee1c47aaa256ecabcaea351eae4a9b01ef39ed810004e298d2511ed284b1525"
+name = "nalgebra"
+version = "0.32.6"
+source = "git+https://git.m-labs.hk/M-Labs/nalgebra.git?rev=ad42410ab0#ad42410ab0abb014229e3ff6bc6ccd39ca92d5d1"
+dependencies = [
+ "approx",
+ "num-complex",
+ "num-rational",
+ "num-traits",
+ "simba",
+ "typenum",
+]
 
 [[package]]
 name = "nb"
@@ -320,44 +407,66 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "546c37ac5d9e56f55e73b677106873d9d9f5190605e41a856503623648488cae"
 
 [[package]]
-name = "num-derive"
-version = "0.3.3"
+name = "num-complex"
+version = "0.4.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "876a53fff98e03a936a674b29568b0e605f06b29372c2489ff4de23f1949743d"
+checksum = "26873667bbbb7c5182d4a37c1add32cdf09f841af72da53318fdb81543c15085"
+dependencies = [
+ "num-traits",
+]
+
+[[package]]
+name = "num-derive"
+version = "0.4.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ed3955f1a9c7c0c15e092f9c887db08b1fc683305fdf6eb6684f22555355e202"
 dependencies = [
  "proc-macro2",
  "quote",
  "syn",
 ]
 
+[[package]]
+name = "num-integer"
+version = "0.1.46"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7969661fd2958a5cb096e56c8e1ad0444ac2bbcd0061bd28660485a44879858f"
+dependencies = [
+ "num-traits",
+]
+
+[[package]]
+name = "num-rational"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d41702bd167c2df5520b384281bc111a4b5efcf7fbc4c9c222c815b07e0a6a6a"
+dependencies = [
+ "autocfg",
+ "num-integer",
+ "num-traits",
+]
+
 [[package]]
 name = "num-traits"
-version = "0.2.14"
+version = "0.2.19"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9a64b1ec5cda2586e284722486d802acf1f7dbdc623e2bfc57e65ca1cd099290"
+checksum = "071dfc062690e90b734c0b2273ce72ad0ffa95f0c74596bc250dcfd960262841"
 dependencies = [
  "autocfg",
+ "libm",
 ]
 
 [[package]]
-name = "pin-project"
-version = "1.0.2"
+name = "paste"
+version = "1.0.15"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9ccc2237c2c489783abd8c4c80e5450fc0e98644555b1364da68cc29aa151ca7"
-dependencies = [
- "pin-project-internal",
-]
+checksum = "57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a"
 
 [[package]]
-name = "pin-project-internal"
-version = "1.0.2"
+name = "pin-project-lite"
+version = "0.2.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f8e8d2bf0b23038a4424865103a4df472855692821aab4e4f5c3312d461d9e5f"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
+checksum = "e0a7ae3ac2f1173085d398531c705756c94a4c56843785df85a60c1a0afac116"
 
 [[package]]
 name = "pin-utils"
@@ -365,32 +474,20 @@ version = "0.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "8b870d8c151b6f2fb93e84a13146138f05d02ed11c7e7c54f8826aaaf7c9f184"
 
-[[package]]
-name = "proc-macro-hack"
-version = "0.5.19"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dbf0c48bc1d91375ae5c3cd81e3722dff1abcf81a30960240640d223f59fe0e5"
-
-[[package]]
-name = "proc-macro-nested"
-version = "0.1.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "eba180dafb9038b050a4c280019bbedf9f2467b61e5d892dcad585bb57aadc5a"
-
 [[package]]
 name = "proc-macro2"
-version = "1.0.24"
+version = "1.0.93"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1e0704ee1a7e00d7bb417d0770ea303c1bccbabf0ef1667dae92b5967f5f8a71"
+checksum = "60946a68e5f9d28b0dc1c21bb8a97ee7d018a8b322fa57838ba31cc878e22d99"
 dependencies = [
- "unicode-xid",
+ "unicode-ident",
 ]
 
 [[package]]
 name = "quote"
-version = "1.0.8"
+version = "1.0.38"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "991431c3519a3f36861882da93630ce66b52918dcf1b8e2fd66b397fc96f28df"
+checksum = "0e4dccaaaf89514f546c693ddc140f729f958c247918a13380cccc6078391acc"
 dependencies = [
  "proc-macro2",
 ]
@@ -406,19 +503,23 @@ name = "runtime"
 version = "0.1.0"
 dependencies = [
  "async-recursion",
+ "build_zynq",
  "byteorder",
  "core_io",
+ "crc",
  "cslice",
  "dwarf",
  "dyld",
  "embedded-hal",
  "futures",
+ "io",
+ "ksupport",
  "libasync",
+ "libboard_artiq",
  "libboard_zynq",
  "libc",
  "libconfig",
  "libcortex_a9",
- "libm",
  "libregister",
  "libsupport_zynq",
  "log",
@@ -426,16 +527,54 @@ dependencies = [
  "nb 0.1.3",
  "num-derive",
  "num-traits",
+ "tar-no-std",
  "unwind",
  "vcell",
  "void",
 ]
 
 [[package]]
-name = "smoltcp"
-version = "0.6.0"
+name = "satman"
+version = "0.0.0"
+dependencies = [
+ "async-recursion",
+ "build_zynq",
+ "byteorder",
+ "core_io",
+ "crc",
+ "cslice",
+ "embedded-hal",
+ "io",
+ "ksupport",
+ "libasync",
+ "libboard_artiq",
+ "libboard_zynq",
+ "libc",
+ "libconfig",
+ "libcortex_a9",
+ "libregister",
+ "libsupport_zynq",
+ "log",
+ "unwind",
+]
+
+[[package]]
+name = "simba"
+version = "0.8.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0fe46639fd2ec79eadf8fe719f237a7a0bd4dac5d957f1ca5bbdbc1c3c39e53a"
+checksum = "50582927ed6f77e4ac020c057f37a268fc6aebc29225050365aacbb9deeeddc4"
+dependencies = [
+ "approx",
+ "num-complex",
+ "num-traits",
+ "paste",
+]
+
+[[package]]
+name = "smoltcp"
+version = "0.7.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3e4a069bef843d170df47e7c0a8bf8d037f217d9f5b325865acc3e466ffe40d3"
 dependencies = [
  "bitflags",
  "byteorder",
@@ -444,36 +583,51 @@ dependencies = [
 
 [[package]]
 name = "syn"
-version = "1.0.55"
+version = "2.0.98"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a571a711dddd09019ccc628e1b17fe87c59b09d513c06c026877aa708334f37a"
+checksum = "36147f1a48ae0ec2b5b3bc5b537d267457555a10dc06f3dbc8cb11ba3006d3b1"
 dependencies = [
  "proc-macro2",
  "quote",
- "unicode-xid",
+ "unicode-ident",
 ]
 
 [[package]]
-name = "unicode-xid"
-version = "0.2.1"
+name = "tar-no-std"
+version = "0.1.8"
+source = "git+https://git.m-labs.hk/M-Labs/tar-no-std?rev=2ab6dc5#2ab6dc58e5249c59c4eb03eaf3a119bcdd678d32"
+dependencies = [
+ "arrayvec",
+ "bitflags",
+ "log",
+]
+
+[[package]]
+name = "typenum"
+version = "1.17.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f7fe0bb3479651439c9112f72b6c505038574c9fbb575ed1bf3b797fa39dd564"
+checksum = "42ff0bf0c66b8238c6f3b578df37d0b7848e55df8577b3f74f92a69acceeb825"
+
+[[package]]
+name = "unicode-ident"
+version = "1.0.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6ceab39d59e4c9499d4e5a8ee0e2735b891bb7308ac83dfb4e80cad195c9f6f3"
 
 [[package]]
 name = "unwind"
 version = "0.0.0"
 dependencies = [
  "cc",
- "cfg-if",
- "compiler_builtins",
+ "cfg-if 0.1.10",
  "libc",
 ]
 
 [[package]]
 name = "vcell"
-version = "0.1.2"
+version = "0.1.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "876e32dcadfe563a4289e994f7cb391197f362b6315dc45e8ba4aa6f564a4b3c"
+checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002"
 
 [[package]]
 name = "void"
@@ -483,9 +637,9 @@ checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
 
 [[package]]
 name = "volatile-register"
-version = "0.2.0"
+version = "0.2.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0d67cb4616d99b940db1d6bd28844ff97108b498a6ca850e5b6191a532063286"
+checksum = "9ee8f19f9d74293faf70901bc20ad067dc1ad390d2cbf1e3f75f721ffee908b6"
 dependencies = [
  "vcell",
 ]

src/Cargo.toml

@@ -3,8 +3,11 @@ members = [
   "libc",
   "libdyld",
   "libdwarf",
+  "libio",
   "libunwind",
+  "libksupport",
   "runtime",
+  "satman"
 ]
 
 [profile.release]
@@ -13,6 +16,3 @@ debug = true
 codegen-units = 1
 opt-level = 2
 lto = true
-
-[patch.crates-io]
-core_io = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }

src/Makefile

@@ -1,21 +1,39 @@
 TARGET := zc706
-VARIANT := simple
+GWARGS := -V nist_clock
 
-all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
+all: runtime
 
-.PHONY: all
+runtime: ../build/runtime.bin
 
+satman: ../build/satman.bin
 
-../build/pl.rs ../build/rustc-cfg: gateware/*
+.PHONY: all manifests
+
+manifests = libboard_artiq/Cargo.toml libc/Cargo.toml libdyld/Cargo.toml libio/Cargo.toml libksupport/Cargo.toml runtime/Cargo.toml satman/Cargo.toml
+
+$(manifests): %.toml: %.toml.tpl
+	sed s+@@ZYNQ_RS@@+$(ZYNQ_RS)+g $< > $@
+
+manifests: $(manifests)
+
+../build/pl.rs ../build/rustc-cfg ../build/mem.rs: gateware/* 
 	mkdir -p ../build
-	python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -V $(VARIANT)
+	python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -m ../build/mem.rs $(GWARGS)
 
-../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg $(shell find . -print)
-	cd runtime && \
-	XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
-	cargo xbuild --release \
-		--target-dir ../../build/firmware \
+../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(manifests) $(shell find . -type f -not -name Cargo.toml -print)
+	cargo build --release \
+	    -p runtime \
+		--target-dir ../build/firmware \
 		--no-default-features --features=target_$(TARGET)
 
 ../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime
 	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
+
+../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(manifests) $(shell find . -type f -not -name Cargo.toml -print)
+	cargo build --release \
+	    -p satman \
+		--target-dir ../build/firmware \
+		--no-default-features --features=target_$(TARGET)
+
+../build/satman.bin: ../build/firmware/armv7-none-eabihf/release/satman
+	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/satman ../build/satman.bin

src/armv7-none-eabihf.json

@@ -1,30 +1,20 @@
 {
-  "abi-blacklist": [
-    "stdcall",
-    "fastcall",
-    "vectorcall",
-    "thiscall",
-    "win64",
-    "sysv64"
-  ],
   "arch": "arm",
   "data-layout": "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64",
   "emit-debug-gdb-scripts": false,
   "env": "",
   "executables": true,
-  "features": "+v7,+vfp3,-d32,+thumb2,-neon",
-  "is-builtin": false,
+  "features": "+v7,+vfp3,-d32,+thumb2,+neon,+a9,+armv7-a",
   "linker": "rust-lld",
   "linker-flavor": "ld.lld",
   "llvm-target": "armv7-unknown-none-eabihf",
+  "llvm-floatabi": "hard",
   "max-atomic-width": 32,
   "os": "none",
   "panic-strategy": "abort",
   "requires-uwtable": true,
-  "force-unwind-tables": "yes",
   "relocation-model": "static",
   "target-c-int-width": "32",
   "target-endian": "little",
-  "target-pointer-width": "32",
-  "vendor": ""
+  "target-pointer-width": "32"
 }

src/gateware/acpki.py

@@ -7,22 +7,28 @@ from misoc.interconnect.csr import *
 
 from artiq.gateware import rtio
 
-OUT_BURST_LEN = 10
-IN_BURST_LEN = 4
+# Burst len defined as number of transfers (0 -> 1, 1 -> 2 ..)
+# thus equal to (64-bit) word count minus one
+FIRST_BURST_LEN = 12 - 1  # extra 2 words for meta
+OUT_BURST_LEN = 10 - 1
+IN_BURST_LEN = 3 - 1
 
+RTIO_I_STATUS_WAIT_STATUS = 4
+RTIO_O_STATUS_WAIT = 1
+
+BATCH_ENTRY_LEN = 80
 
 class Engine(Module, AutoCSR):
     def __init__(self, bus, user):
-        self.addr_base = CSRStorage(32)
-        self.trig_count = CSRStatus(32)
-        self.write_count = CSRStatus(32)
+        self.addr_base = Signal(32)
+        self.write_addr = Signal(32)
 
         self.trigger_stb = Signal()
 
         # Dout : Data received from CPU, output by DMA module
         # Din : Data driven into DMA module, written into CPU
-        # When stb assert, index shows word being read/written, dout/din holds
-        # data
+        # When stb is asserted, index shows word being read/written, 
+        # dout/din holds data
         #
         # Cycle:
         # trigger_stb pulsed at start
@@ -35,11 +41,10 @@ class Engine(Module, AutoCSR):
         self.din_ready = Signal()
         self.dout = Signal(64)
         self.din = Signal(64)
+        self.dout_burst_len = Signal(4)
 
         ###
 
-        self.sync += If(self.trigger_stb, self.trig_count.status.eq(self.trig_count.status+1))
-
         self.comb += [
             user.aruser.eq(0x1f),
             user.awuser.eq(0x1f)
@@ -49,12 +54,12 @@ class Engine(Module, AutoCSR):
 
         ### Read
         self.comb += [
-            ar.addr.eq(self.addr_base.storage),
+            ar.addr.eq(self.addr_base),
             self.dout.eq(r.data),
             r.ready.eq(1),
             ar.burst.eq(axi.Burst.incr.value),
-            ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
-            ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
+            ar.len.eq(self.dout_burst_len),
+            ar.size.eq(3),  # Width of burst: 3 = 8 bytes = 64 bits
             ar.cache.eq(0xf),
         ]
 
@@ -86,22 +91,23 @@ class Engine(Module, AutoCSR):
         self.sync += [
             If(read_fsm.ongoing("IDLE"),
                 self.dout_index.eq(0)
-            ).Else(If(r.valid & read_fsm.ongoing("READ"),
-                    self.dout_index.eq(self.dout_index+1)
-                )
+            ).Elif(r.valid & read_fsm.ongoing("READ"),
+                self.dout_index.eq(self.dout_index+1)
             )
         ]
 
         self.comb += self.dout_stb.eq(r.valid & r.ready)
+        self.read_idle = Signal()
+        self.comb += self.read_idle.eq(read_fsm.ongoing("IDLE"))
 
         ### Write
         self.comb += [
             w.data.eq(self.din),
-            aw.addr.eq(self.addr_base.storage+96),
+            aw.addr.eq(self.write_addr),
             w.strb.eq(0xff),
             aw.burst.eq(axi.Burst.incr.value),
-            aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
-            aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
+            aw.len.eq(IN_BURST_LEN),  # Number of transfers in burst minus 1
+            aw.size.eq(3),  # Width of burst: 3 = 8 bytes = 64 bits
             aw.cache.eq(0xf),
             b.ready.eq(1),
         ]
@@ -113,7 +119,7 @@ class Engine(Module, AutoCSR):
             aw.valid.eq(0),
             If(self.trigger_stb,
                 aw.valid.eq(1),
-                If(aw.ready, # assumes aw.ready is not randomly deasserted
+                If(aw.ready,  # assumes aw.ready is not deasserted from now on
                     NextState("DATA_WAIT")
                 ).Else(
                     NextState("AW_READY_WAIT")
@@ -140,8 +146,6 @@ class Engine(Module, AutoCSR):
             )
         )
 
-        self.sync += If(w.ready & w.valid, self.write_count.status.eq(self.write_count.status+1))
-
         self.sync += [
             If(write_fsm.ongoing("IDLE"),
                 self.din_index.eq(0)
@@ -150,18 +154,20 @@ class Engine(Module, AutoCSR):
         ]
 
         self.comb += [
-            w.last.eq(0),
-            If(self.din_index==aw.len, w.last.eq(1))
+            w.last.eq(self.din_index==aw.len),
+            self.din_stb.eq(w.valid & w.ready)
         ]
 
-        self.comb += self.din_stb.eq(w.valid & w.ready)
-
-
+        self.write_idle = Signal()
+        self.comb += self.write_idle.eq(write_fsm.ongoing("IDLE"))
 
 class KernelInitiator(Module, AutoCSR):
     def __init__(self, tsc, bus, user, evento):
         # Core is disabled upon reset to avoid spurious triggering if evento toggles from e.g. boot code.
+        # Should be also reset between kernels (?)
         self.enable = CSRStorage()
+        self.out_base = CSRStorage(32)  # output data (to CRI)
+        self.in_base = CSRStorage(32)   # in data (RTIO reply)
 
         self.counter = CSRStatus(64)
         self.counter_update = CSR()
@@ -173,12 +179,22 @@ class KernelInitiator(Module, AutoCSR):
 
         ###
 
+        batch_en = Signal()
+
+        batch_offset = Signal.like(self.out_base.storage)   # address offset
+        batch_len = Signal(32)
+        batch_ptr = Signal(32)
+        batch_stb = Signal()  # triggers the next event in the batch
+
         evento_stb = Signal()
         evento_latched = Signal()
         evento_latched_d = Signal()
         self.specials += MultiReg(evento, evento_latched)
         self.sync += evento_latched_d.eq(evento_latched)
-        self.comb += self.engine.trigger_stb.eq(self.enable.storage & (evento_latched != evento_latched_d))
+        self.comb += [
+            self.engine.trigger_stb.eq(self.enable.storage & ((evento_latched != evento_latched_d) | batch_stb)),
+            self.engine.write_addr.eq(self.in_base.storage),
+        ]
 
         cri = self.cri
 
@@ -186,77 +202,130 @@ class KernelInitiator(Module, AutoCSR):
         cmd_write = Signal()
         cmd_read = Signal()
         self.comb += [
-            cmd_write.eq(cmd == 0),
-            cmd_read.eq(cmd == 1)
+            cmd_write.eq(batch_en | (cmd == 0)),  # rtio output, forced in batch mode
+            cmd_read.eq(~batch_en & (cmd == 1)),  # rtio input, disallowed in batch mode
         ]
 
         out_len = Signal(8)
         dout_cases = {}
         dout_cases[0] = [
-            cmd.eq(self.engine.dout[:8]),
-            out_len.eq(self.engine.dout[8:16]),
-            cri.chan_sel.eq(self.engine.dout[40:]),
-            cri.o_address.eq(self.engine.dout[32:40])
+            cmd.eq(self.engine.dout[:8]),               # request_cmd: i8
+            out_len.eq(self.engine.dout[8:16]),         # data_width: i8
+            # padding (2 bytes)
+            cri.o_address.eq(self.engine.dout[32:40]),  # request_target: i32
+            cri.chan_sel.eq(self.engine.dout[40:]),     # request_target cont.
         ]
         for i in range(8):
             target = cri.o_data[i*64:(i+1)*64]
             dout_cases[0] += [If(i >= self.engine.dout[8:16], target.eq(0))]
 
         dout_cases[1] = [
-            cri.o_timestamp.eq(self.engine.dout),
-            cri.i_timeout.eq(self.engine.dout)
+            cri.o_timestamp.eq(self.engine.dout),  # request_timestamp: i64
+            cri.i_timeout.eq(self.engine.dout),
         ]
         for i in range(8):
-            target = cri.o_data[i*64:(i+1)*64]
+            target = cri.o_data[i*64:(i+1)*64] # request_data: [i32; 16]
             dout_cases[i+2] = [target.eq(self.engine.dout)]
 
+        # first iteration has extra 8 bytes for metadata
+        first_iter = Signal()
         self.sync += [
             cri.cmd.eq(rtio.cri.commands["nop"]),
             If(self.engine.dout_stb,
-                Case(self.engine.dout_index, dout_cases),
-                If(self.engine.dout_index == out_len + 2,
-                    If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])),
-                    If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"]))
-                )
+                If(first_iter,
+                    # manual case for metadata
+                    If(self.engine.dout_index == 0,
+                        batch_len.eq(self.engine.dout[:32]),
+                        batch_en.eq(self.engine.dout[32:40] == 1),
+                    ).Elif(self.engine.dout_index >= 2,
+                        Case(self.engine.dout_index-2, dout_cases)
+                    ),
+                    If(self.engine.dout_index == out_len + 4,
+                        If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])),
+                        If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"]))
+                    )
+                ).Else(
+                    Case(self.engine.dout_index, dout_cases),
+                    If(self.engine.dout_index == out_len + 2,
+                        If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])),
+                        If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"]))
+                    )
+                ),
             )
         ]
 
-        # If input event, wait for response before allow input data to be
-        # sampled
-        # TODO: If output, wait for wait flag clear
-        RTIO_I_STATUS_WAIT_STATUS = 4
-        RTIO_O_STATUS_WAIT = 1
+        # If input event, wait for response before 
+        # allowing the input data to be sampled
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
 
         fsm.act("IDLE",
-            If(self.engine.trigger_stb, NextState("WAIT_OUT_CYCLE"))
+            If(self.engine.trigger_stb,
+                NextState("FIRST_WAIT")),
         )
-        fsm.act("WAIT_OUT_CYCLE",
+        fsm.act("FIRST_WAIT",
+            # first cycle - with extra 16 bytes for metadata
             self.engine.din_ready.eq(0),
-            If(self.engine.dout_stb & cmd_write & (self.engine.dout_index == out_len + 2),
-               NextState("WAIT_READY")
-            ),
-            # for some reason read requires some delay until the next state
-            If(self.engine.dout_stb & cmd_read & (self.engine.dout_index == out_len + 3),
+            batch_stb.eq(0),
+            first_iter.eq(1),
+            If(self.engine.dout_stb & (self.engine.dout_index == out_len + 5),
+                # prepare for the next step (no metadata for the next iterations)
+                If(batch_en,
+                    NextValue(batch_ptr, batch_ptr + 1),
+                    NextValue(self.engine.addr_base, self.engine.addr_base + BATCH_ENTRY_LEN + 16),
+                    NextValue(self.engine.dout_burst_len, OUT_BURST_LEN),
+                ),
                 NextState("WAIT_READY")
             )
         )
-        fsm.act("WAIT_READY",
-            If(cmd_read & (cri.i_status & RTIO_I_STATUS_WAIT_STATUS == 0) \
-                | cmd_write & ~(cri.o_status & RTIO_O_STATUS_WAIT),
-                self.engine.din_ready.eq(1),
-                NextState("IDLE")
+        fsm.act("BATCH_NEXT_CYCLE",
+            self.engine.din_ready.eq(0),
+            batch_stb.eq(0),
+            first_iter.eq(0),
+            If(self.engine.dout_stb & (self.engine.dout_index == out_len + 3),
+                If(batch_en,
+                    NextValue(batch_ptr, batch_ptr + 1),
+                    NextValue(self.engine.addr_base, self.engine.addr_base + BATCH_ENTRY_LEN)
+                ),
+                NextState("WAIT_READY")
             )
         )
 
+        fsm.act("WAIT_READY",
+            batch_stb.eq(0),
+            If((cmd_read & (cri.i_status & RTIO_I_STATUS_WAIT_STATUS == 0)) \
+                | (cmd_write & (cri.o_status & RTIO_O_STATUS_WAIT == 0)),
+                # stop the batch in case of an error or when reaching the capacity
+                If(~batch_en |
+                    (batch_en & (((batch_len - 1) == batch_ptr) | (cri.o_status != 0))),
+                    self.engine.din_ready.eq(1),
+                    NextState("IDLE")
+                ).Elif(self.engine.read_idle,
+                    batch_stb.eq(1),
+                    NextState("BATCH_NEXT_CYCLE")
+                )
+            )
+        )
+
+        self.sync += [
+            If(fsm.ongoing("IDLE"),
+                batch_ptr.eq(0),
+                batch_offset.eq(0),
+                self.engine.addr_base.eq(self.out_base.storage),
+                self.engine.dout_burst_len.eq(FIRST_BURST_LEN),
+            ),
+        ]
+
         din_cases_cmdwrite = {
             0: [self.engine.din.eq((1<<16) | cri.o_status)],
             1: [self.engine.din.eq(0)],
+            2: [self.engine.din.eq(batch_ptr)]
         }
         din_cases_cmdread = {
+            # reply_status: VolatileCell<i32>, reply_data: VolatileCell<i32>
             0: [self.engine.din[:32].eq((1<<16) | cri.i_status), self.engine.din[32:].eq(cri.i_data)],
-            1: [self.engine.din.eq(cri.i_timestamp)]
+            1: [self.engine.din.eq(cri.i_timestamp)],  # reply_timestamp: VolatileCell<i64>,
+            2: [self.engine.din.eq(batch_ptr)]     # reply_batch_count: VolatileCell<i32>
         }
 
         self.comb += [

src/gateware/config.py

@@ -0,0 +1,26 @@
+import os
+from artiq._version import get_version
+from misoc.integration import cpu_interface
+
+
+def generate_ident(variant):
+    return "{}+{};{}".format(
+        get_version().split(".")[0],
+        os.getenv("ZYNQ_REV", default="unknown")[:8],
+        variant,
+    )
+
+def write_csr_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_csr_rust(
+            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
+
+def write_mem_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_mem_rust(
+            soc.get_memory_regions(), soc.get_memory_groups(), None))
+
+def write_rustc_cfg_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_rust_cfg(
+            soc.get_csr_regions(), soc.get_constants()))

src/gateware/coraz7.py

@@ -1,191 +0,0 @@
-#!/usr/bin/env python
-
-import argparse
-from operator import itemgetter
-
-from migen import *
-from migen.build.generic_platform import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.cdc import MultiReg
-from migen_axi.integration.soc_core import SoCCore
-from migen_axi.platforms import coraz7
-from misoc.interconnect.csr import *
-from misoc.integration import cpu_interface
-
-from artiq.gateware import rtio
-from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
-
-import dma
-import analyzer
-import acpki
-
-
-class RTIOCRG(Module, AutoCSR):
-    def __init__(self, platform, rtio_internal_clk):
-        self.clock_sel = CSRStorage()
-        self.pll_reset = CSRStorage(reset=1)
-        self.pll_locked = CSRStatus()
-        self.clock_domains.cd_rtio = ClockDomain()
-        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
-
-        rtio_external_clk = Signal()
-        # user_sma_clock = platform.request("user_sma_clock")
-        # platform.add_period_constraint(user_sma_clock.p, 8.0)
-        # self.specials += Instance("IBUFDS",
-        #                           i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
-        #                           o_O=rtio_external_clk)
-
-        pll_locked = Signal()
-        rtio_clk = Signal()
-        rtiox4_clk = Signal()
-        self.specials += [
-            Instance("PLLE2_ADV",
-                     p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
-
-                     p_REF_JITTER1=0.01,
-                     p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
-                     i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
-                     # Warning: CLKINSEL=0 means CLKIN2 is selected
-                     i_CLKINSEL=~self.clock_sel.storage,
-
-                     # VCO @ 1GHz when using 125MHz input
-                     p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
-                     i_CLKFBIN=self.cd_rtio.clk,
-                     i_RST=self.pll_reset.storage,
-
-                     o_CLKFBOUT=rtio_clk,
-
-                     p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
-                     o_CLKOUT0=rtiox4_clk),
-            Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
-            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
-            AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
-            MultiReg(pll_locked, self.pll_locked.status)
-        ]
-
-
-class CoraZ7(SoCCore):
-    def __init__(self, device_variant="10", acpki=False):
-        self.acpki = acpki
-        self.rustc_cfg = dict()
-
-        platform = coraz7.Platform(device_variant=device_variant)
-        platform.toolchain.bitstream_commands.extend([
-            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
-        ])
-        ident = self.__class__.__name__
-        if self.acpki:
-            ident = "acpki_" + ident
-        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
-
-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
-        self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
-        self.csr_devices.append("rtio_crg")
-        self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
-        self.platform.add_false_path_constraints(
-            self.ps7.cd_sys.clk,
-            self.rtio_crg.cd_rtio.clk)
-
-    def add_rtio(self, rtio_channels):
-        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
-        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
-        self.csr_devices.append("rtio_core")
-
-        if self.acpki:
-            self.rustc_cfg["ki_impl"] = "acp"
-            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                         bus=self.ps7.s_axi_acp,
-                                                         user=self.ps7.s_axi_acp_user,
-                                                         evento=self.ps7.event.o)
-            self.csr_devices.append("rtio")
-        else:
-            self.rustc_cfg["ki_impl"] = "csr"
-            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
-            self.csr_devices.append("rtio")
-
-        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
-        self.csr_devices.append("rtio_dma")
-
-        self.submodules.cri_con = rtio.CRIInterconnectShared(
-            [self.rtio.cri, self.rtio_dma.cri],
-            [self.rtio_core.cri])
-        self.csr_devices.append("cri_con")
-
-        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
-        self.csr_devices.append("rtio_moninj")
-
-        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
-                                                          self.ps7.s_axi_hp1)
-        self.csr_devices.append("rtio_analyzer")
-
-
-class Simple(CoraZ7):
-    def __init__(self, **kwargs):
-        CoraZ7.__init__(self, **kwargs)
-
-        platform = self.platform
-
-        rtio_channels = []
-        for i in range(2):
-            phy = ttl_simple.Output(platform.request("user_led", i))
-            self.submodules += phy
-            rtio_channels.append(rtio.Channel.from_phy(phy))
-
-        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
-        rtio_channels.append(rtio.LogChannel())
-
-        self.add_rtio(rtio_channels)
-
-
-def write_csr_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_csr_rust(
-            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
-
-
-def write_rustc_cfg_file(soc, filename):
-    with open(filename, "w") as f:
-        for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
-            if v is None:
-                f.write("{}\n".format(k))
-            else:
-                f.write("{}=\"{}\"\n".format(k, v))
-
-
-def main():
-    parser = argparse.ArgumentParser(
-        description="ARTIQ port to the Cora Z7 Zynq development kit")
-    parser.add_argument("-r", default=None,
-        help="build Rust interface into the specified file")
-    parser.add_argument("-c", default=None,
-        help="build Rust compiler configuration into the specified file")
-    parser.add_argument("-g", default=None,
-        help="build gateware into the specified directory")
-    parser.add_argument("-V", "--variant", default="10",
-                        help="variant: "
-                             "[acpki_]10/07s "
-                             "(default: %(default)s)")
-    args = parser.parse_args()
-
-    variant = args.variant.lower()
-    acpki = variant.startswith("acpki_")
-    if acpki:
-        variant = variant[6:]
-    try:
-        soc = Simple(device_variant=variant, acpki=acpki)
-    except KeyError:
-        raise SystemExit("Invalid variant (-V/--variant)")
-    soc.finalize()
-
-    if args.r is not None:
-        write_csr_file(soc, args.r)
-    if args.c is not None:
-        write_rustc_cfg_file(soc, args.c)
-    if args.g is not None:
-        soc.build(build_dir=args.g)
-
-
-if __name__ == "__main__":
-    main()

src/gateware/cxp_4r_fmc.py

@@ -0,0 +1,74 @@
+from migen.build.generic_platform import *
+
+fmc_adapter_io = [
+    # CoaXPress high speed link
+    ("CXP_HS", 0,
+        Subsignal("rxp", Pins("HPC:DP0_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP0_M2C_N")),
+    ),
+    ("CXP_HS", 1,
+        Subsignal("rxp", Pins("HPC:DP1_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP1_M2C_N")),
+    ),
+    ("CXP_HS", 2,
+        Subsignal("rxp", Pins("HPC:DP2_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP2_M2C_N")),
+    ),
+    ("CXP_HS", 3,
+        Subsignal("rxp", Pins("HPC:DP3_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP3_M2C_N")),
+    ),
+
+    # CoaXPress low speed link
+    ("CXP_LS", 0, Pins("HPC:LA00_CC_P"), IOStandard("LVCMOS33")),
+    ("CXP_LS", 1, Pins("HPC:LA01_CC_N"), IOStandard("LVCMOS33")),
+    ("CXP_LS", 2, Pins("HPC:LA01_CC_P"), IOStandard("LVCMOS33")),
+    ("CXP_LS", 3, Pins("HPC:LA02_N"), IOStandard("LVCMOS33")),
+
+    # CoaXPress green and red LED
+    ("CXP_LED", 0,
+        Subsignal("green", Pins("HPC:LA11_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA11_N"), IOStandard("LVCMOS33")),
+    ),
+    ("CXP_LED", 1,
+        Subsignal("green", Pins("HPC:LA12_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA12_N"), IOStandard("LVCMOS33")),
+    ),
+    ("CXP_LED", 2,
+        Subsignal("green", Pins("HPC:LA13_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA13_N"), IOStandard("LVCMOS33")),
+    ),
+    ("CXP_LED", 3,
+        Subsignal("green", Pins("HPC:LA14_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA14_N"), IOStandard("LVCMOS33")),
+    ),
+
+    # Power over CoaXPress 
+    ("PoCXP", 0,
+        Subsignal("enable", Pins("HPC:LA21_N"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA18_CC_P"), IOStandard("LVCMOS33")),
+    ),
+    ("PoCXP", 1,
+        Subsignal("enable", Pins("HPC:LA21_P"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA19_N"), IOStandard("LVCMOS33")),
+    ),
+    ("PoCXP", 2,
+        Subsignal("enable", Pins("HPC:LA22_N"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA19_P"), IOStandard("LVCMOS33")),
+    ),
+    ("PoCXP", 3,
+        Subsignal("enable", Pins("HPC:LA22_P"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA20_N"), IOStandard("LVCMOS33")),
+    ),
+    ("i2c", 0,
+        Subsignal("scl", Pins("HPC:IIC_SCL")),
+        Subsignal("sda", Pins("HPC:IIC_SDA")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # On board 125MHz reference 
+    ("clk125", 0,
+        Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
+        Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),
+    ),
+]

src/gateware/ddmtd.py

@@ -0,0 +1,119 @@
+from migen import *
+from migen.genlib.cdc import PulseSynchronizer, MultiReg
+from misoc.interconnect.csr import *
+
+
+class DDMTDSampler(Module):
+    def __init__(self, cd_ref, main_clk_se):
+        self.ref_beating = Signal()
+        self.main_beating = Signal()
+
+        # # #
+
+        ref_clk = Signal()
+        self.specials +=[
+            # ISERDESE2 can only be driven from fabric via IDELAYE2 (see UG471)
+            Instance("IDELAYE2",
+                    p_DELAY_SRC="DATAIN",
+                    p_HIGH_PERFORMANCE_MODE="TRUE",
+                    p_REFCLK_FREQUENCY=208.3,   # REFCLK frequency from IDELAYCTRL
+                    p_IDELAY_VALUE=0,
+
+                    i_DATAIN=cd_ref.clk,
+
+                    o_DATAOUT=ref_clk
+            ),
+            Instance("ISERDESE2",
+                    p_IOBDELAY="IFD",   # use DDLY as input
+                    p_DATA_RATE="SDR",
+                    p_DATA_WIDTH=2,     # min is 2
+                    p_NUM_CE=1,
+
+                    i_DDLY=ref_clk,
+                    i_CE1=1,
+                    i_CLK=ClockSignal("helper"),
+                    i_CLKDIV=ClockSignal("helper"),
+
+                    o_Q1=self.ref_beating
+            ),
+            Instance("ISERDESE2",
+                    p_DATA_RATE="SDR",
+                    p_DATA_WIDTH=2,     # min is 2
+                    p_NUM_CE=1,
+
+                    i_D=main_clk_se,
+                    i_CE1=1,
+                    i_CLK=ClockSignal("helper"),
+                    i_CLKDIV=ClockSignal("helper"),
+
+                    o_Q1=self.main_beating,
+            ),
+        ]
+
+
+class DDMTDDeglitcherMedianEdge(Module):
+    def __init__(self, counter, input_signal, stable_0_period=100, stable_1_period=100):
+        self.tag = Signal(len(counter))
+        self.detect = Signal()
+
+        stable_0_counter = Signal(reset=stable_0_period - 1, max=stable_0_period)
+        stable_1_counter = Signal(reset=stable_1_period - 1, max=stable_1_period)
+
+        # # #
+
+        # Based on CERN's median edge deglitcher FSM
+        # https://white-rabbit.web.cern.ch/documents/Precise_time_and_frequency_transfer_in_a_White_Rabbit_network.pdf (p.72)
+        fsm = ClockDomainsRenamer("helper")(FSM(reset_state="WAIT_STABLE_0"))
+        self.submodules += fsm
+
+        fsm.act("WAIT_STABLE_0",
+            If(stable_0_counter != 0,
+                NextValue(stable_0_counter, stable_0_counter - 1)
+            ).Else(
+                NextValue(stable_0_counter, stable_0_period - 1),
+                NextState("WAIT_EDGE")
+            ),
+            If(input_signal,
+                NextValue(stable_0_counter, stable_0_period - 1)
+            ),
+        )
+        fsm.act("WAIT_EDGE",
+            If(input_signal,
+                NextValue(self.tag, counter),
+                NextState("GOT_EDGE")
+            )
+        )
+        fsm.act("GOT_EDGE",
+            If(stable_1_counter != 0,
+                NextValue(stable_1_counter, stable_1_counter - 1)
+            ).Else(
+                NextValue(stable_1_counter, stable_1_period - 1),
+                self.detect.eq(1),
+                NextState("WAIT_STABLE_0")
+            ),
+            If(~input_signal,
+                NextValue(self.tag, self.tag + 1),
+                NextValue(stable_1_counter, stable_1_period - 1)
+            ),
+        )
+        
+
+class DDMTD(Module):
+    def __init__(self, counter, input_signal):
+
+        # in helper clock domain
+        self.h_tag = Signal(len(counter))
+        self.h_tag_update = Signal()
+
+        # # #
+
+        deglitcher = DDMTDDeglitcherMedianEdge(counter, input_signal)
+        self.submodules += deglitcher
+
+        self.sync.helper += [
+            self.h_tag_update.eq(0),
+            If(deglitcher.detect,
+                self.h_tag_update.eq(1),
+                self.h_tag.eq(deglitcher.tag)
+               )
+        ]

src/gateware/drtio_aux_controller.py

@@ -0,0 +1,85 @@
+"""Auxiliary controller, common to satellite and master"""
+
+from artiq.gateware.drtio.aux_controller import (max_packet, aux_buffer_count,
+    Transmitter, Receiver)
+from migen.fhdl.simplify import FullMemoryWE
+from misoc.interconnect.csr import *
+from migen_axi.interconnect.sram import SRAM
+from migen_axi.interconnect import axi
+
+
+class _DRTIOAuxControllerBase(Module):
+    def __init__(self, link_layer):
+        self.bus = axi.Interface()
+        self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
+        self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
+
+    def get_csrs(self):
+        return self.transmitter.get_csrs() + self.receiver.get_csrs()
+
+
+# TODO: FullMemoryWE should be applied by migen.build
+@FullMemoryWE()
+class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
+    def __init__(self, link_layer):
+        _DRTIOAuxControllerBase.__init__(self, link_layer)
+
+        tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
+        rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
+        aw_decoder = axi.AddressDecoder(self.bus.aw,
+            [(lambda a: a[log2_int(max_packet*aux_buffer_count)] == 0, tx_sdram_if.bus.aw),
+             (lambda a: a[log2_int(max_packet*aux_buffer_count)] == 1, rx_sdram_if.bus.aw)],
+            register=True)
+        ar_decoder = axi.AddressDecoder(self.bus.ar,
+            [(lambda a: a[log2_int(max_packet*aux_buffer_count)] == 0, tx_sdram_if.bus.ar),
+             (lambda a: a[log2_int(max_packet*aux_buffer_count)] == 1, rx_sdram_if.bus.ar)],
+            register=True)
+        # unlike wb, axi address decoder only connects ar/aw lanes,
+        # the rest must also be connected!
+        # not quite unlike an address decoder itself.
+
+        # connect bus.b with tx.b
+        self.comb += [tx_sdram_if.bus.b.ready.eq(self.bus.b.ready),
+                      self.bus.b.id.eq(tx_sdram_if.bus.b.id),
+                      self.bus.b.resp.eq(tx_sdram_if.bus.b.resp),
+                      self.bus.b.valid.eq(tx_sdram_if.bus.b.valid)]
+        # connect bus.w with tx.w
+        # no worries about w.valid and slave sel here, only tx will be written to
+        self.comb += [tx_sdram_if.bus.w.id.eq(self.bus.w.id),
+                      tx_sdram_if.bus.w.data.eq(self.bus.w.data),
+                      tx_sdram_if.bus.w.strb.eq(self.bus.w.strb),
+                      tx_sdram_if.bus.w.last.eq(self.bus.w.last),
+                      tx_sdram_if.bus.w.valid.eq(self.bus.w.valid),
+                      self.bus.w.ready.eq(tx_sdram_if.bus.w.ready)]
+        # connect bus.r with rx.r and tx.r w/o data
+        self.comb += [self.bus.r.id.eq(rx_sdram_if.bus.r.id | tx_sdram_if.bus.r.id),
+                #self.bus.r.data.eq(rx_sdram_if.bus.r.data | tx_sdram_if.bus.r.data),
+                self.bus.r.resp.eq(rx_sdram_if.bus.r.resp | tx_sdram_if.bus.r.resp),
+                self.bus.r.last.eq(rx_sdram_if.bus.r.last | tx_sdram_if.bus.r.last),
+                self.bus.r.valid.eq(rx_sdram_if.bus.r.valid | tx_sdram_if.bus.r.valid),
+                rx_sdram_if.bus.r.ready.eq(self.bus.r.ready),
+                tx_sdram_if.bus.r.ready.eq(self.bus.r.ready)]
+        # connect read data after being masked
+        masked = [Replicate(rx_sdram_if.bus.r.valid,
+                            len(self.bus.r.data)
+                            ) & rx_sdram_if.bus.r.data,
+                 Replicate(tx_sdram_if.bus.r.valid,
+                            len(self.bus.r.data)
+                            ) & tx_sdram_if.bus.r.data]
+        self.comb += self.bus.r.data.eq(reduce(or_, masked))
+
+        self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder
+
+
+@FullMemoryWE()
+class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
+    # Barebones version of the AuxController. No SRAM, no decoders.
+    # add memories manually from tx and rx in target code.
+    def get_tx_port(self):
+        return self.transmitter.mem.get_port(write_capable=True)
+
+    def get_rx_port(self):
+        return self.receiver.mem.get_port(write_capable=False)
+
+    def get_mem_size(self):
+        return max_packet*aux_buffer_count

src/gateware/ebaz4205.py

@@ -0,0 +1,309 @@
+#!/usr/bin/env python
+
+import argparse
+
+import analyzer
+import dma
+from artiq.gateware import rtio
+from artiq.gateware.rtio.phy import spi2, ttl_simple
+from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
+from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
+from migen import *
+from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal
+from migen.build.platforms import ebaz4205
+from migen_axi.integration.soc_core import SoCCore
+from misoc.interconnect.csr import *
+
+_ps = [
+    (
+        "ps",
+        0,
+        Subsignal("clk", Pins("E7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
+        Subsignal("por_b", Pins("C7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
+        Subsignal("srst_b", Pins("B10"), IOStandard("LVCMOS18"), Misc("SLEW=FAST")),
+    )
+]
+
+_ddr = [
+    (
+        "ddr",
+        0,
+        Subsignal(
+            "a",
+            Pins("N2 K2 M3 K3 M4 L1 L4 K4 K1 J4 F5 G4 E4 D4 F4"),
+            IOStandard("SSTL15"),
+        ),
+        Subsignal("ba", Pins("L5 R4 J5"), IOStandard("SSTL15")),
+        Subsignal("cas_n", Pins("P5"), IOStandard("SSTL15")),
+        Subsignal("cke", Pins("N3"), IOStandard("SSTL15")),
+        Subsignal("cs_n", Pins("N1"), IOStandard("SSTL15")),
+        Subsignal("ck_n", Pins("M2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")),
+        Subsignal("ck_p", Pins("L2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")),
+        # Pins "T1 Y1" not connected
+        Subsignal("dm", Pins("A1 F1"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
+        Subsignal(
+            "dq",
+            Pins("C3 B3 A2 A4 D3 D1 C1 E1 E2 E3 G3 H3 J3 H2 H1 J1"),
+            # Pins "P1 P3 R3 R1 T4 U4 U2 U3 V1 Y3 W1 Y4 Y2 W3 V2 V3" not connected
+            IOStandard("SSTL15_T_DCI"),
+            Misc("SLEW=FAST"),
+        ),
+        Subsignal(
+            "dqs_n",
+            Pins("B2 F2"),  # Pins "T2 W4" not connected
+            IOStandard("DIFF_SSTL15_T_DCI"),
+            Misc("SLEW=FAST"),
+        ),
+        Subsignal(
+            "dqs_p",
+            Pins("C2 G2"),  # Pins "R2 W5" not connected
+            IOStandard("DIFF_SSTL15_T_DCI"),
+            Misc("SLEW=FAST"),
+        ),
+        Subsignal("vrn", Pins("G5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
+        Subsignal("vrp", Pins("H5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
+        Subsignal("drst_n", Pins("B4"), IOStandard("SSTL15"), Misc("SLEW=FAST")),
+        Subsignal("odt", Pins("N5"), IOStandard("SSTL15")),
+        Subsignal("ras_n", Pins("P4"), IOStandard("SSTL15")),
+        Subsignal("we_n", Pins("M5"), IOStandard("SSTL15")),
+    )
+]
+
+# Connector J3
+_i2c = [
+    (
+        "i2c",
+        0,
+        Subsignal("scl", Pins("U12"), IOStandard("LVCMOS33")),
+        Subsignal("sda", Pins("V13"), IOStandard("LVCMOS33")),
+    )
+]
+
+_spi = [
+    (
+        "spi",
+        0,
+        Subsignal("clk", Pins("V20")),
+        Subsignal("mosi", Pins("U20")),
+        Subsignal("cs_n", Pins("P19")),
+        IOStandard("LVCMOS33"),
+    )
+]
+
+
+# Connector DATA1
+def _create_ttl():
+    _ttl = []
+
+    for idx, elem in enumerate([x for x in range(5, 21) if x not in (10, 12)]):
+        _ttl.append(
+            ("ttl", idx, Pins("DATA1:DATA1-{}".format(elem)), IOStandard("LVCMOS33")),
+        )
+    return _ttl
+
+
+class EBAZ4205(SoCCore):
+    def __init__(self, rtio_clk=125e6, acpki=False, acpki_batch_size=1e5):
+        self.acpki = acpki
+
+        platform = ebaz4205.Platform()
+        platform.toolchain.bitstream_commands.extend(
+            [
+                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+            ]
+        )
+        platform.add_extension(_ps)
+        platform.add_extension(_ddr)
+        platform.add_extension(_i2c)
+        platform.add_extension(_spi)
+        platform.add_extension(_create_ttl())
+
+        gmii = platform.request("gmii")
+        platform.add_period_constraint(gmii.rx_clk, 10)
+        platform.add_period_constraint(gmii.tx_clk, 10)
+        platform.add_platform_command(
+            "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
+        )
+
+        ident = generate_ident(self.__class__.__name__)
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
+        fix_serdes_timing_path(platform)
+        self.config["RTIO_FREQUENCY"] = str(rtio_clk / 1e6)
+        platform.add_period_constraint(self.ps7.cd_sys.clk, 10)
+
+        self.comb += [
+            self.ps7.enet0.enet.gmii.tx_clk.eq(gmii.tx_clk),
+            self.ps7.enet0.enet.gmii.rx_clk.eq(gmii.rx_clk),
+        ]
+        self.clock_domains.cd_eth_rx = ClockDomain(reset_less=False)
+        self.clock_domains.cd_eth_tx = ClockDomain(reset_less=False)
+        self.comb += [
+            ClockSignal("eth_rx").eq(gmii.rx_clk),
+            ClockSignal("eth_tx").eq(gmii.tx_clk),
+        ]
+        self.sync.eth_tx += [
+            gmii.txd.eq(self.ps7.enet0.enet.gmii.txd),
+            gmii.tx_en.eq(self.ps7.enet0.enet.gmii.tx_en),
+        ]
+        self.sync.eth_rx += [
+            self.ps7.enet0.enet.gmii.rxd.eq(gmii.rxd),
+            self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
+        ]
+
+        # MDIO
+        mdio = platform.request("mdio")
+        self.comb += mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc)
+        self.specials += Instance(
+            "IOBUF",
+            i_I=self.ps7.enet0.enet.mdio.o,
+            io_IO=mdio.mdio,
+            o_O=self.ps7.enet0.enet.mdio.i,
+            i_T=~self.ps7.enet0.enet.mdio.t_n,
+        )
+
+        # I2C
+        i2c = self.platform.request("i2c")
+        self.specials += [
+            # SCL
+            Instance(
+                "IOBUF",
+                i_I=self.ps7.i2c0.scl.o,
+                io_IO=i2c.scl,
+                o_O=self.ps7.i2c0.scl.i,
+                i_T=~self.ps7.i2c0.scl.t_n,
+            ),
+            # SDA
+            Instance(
+                "IOBUF",
+                i_I=self.ps7.i2c0.sda.o,
+                io_IO=i2c.sda,
+                o_O=self.ps7.i2c0.sda.i,
+                i_T=~self.ps7.i2c0.sda.t_n,
+            ),
+        ]
+
+        self.rtio_channels = []
+        for i in (0, 1):
+            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            user_led = self.platform.request("user_led", i)
+            phy = ttl_simple.Output(user_led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        for i in range(14):
+            print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            ttl = self.platform.request("ttl", i)
+            phy = ttl_simple.InOut(ttl)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        print("SPI at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+        spi_phy = spi2.SPIMaster(platform.request("spi"))
+        self.submodules += spi_phy
+        self.rtio_channels.append(rtio.Channel.from_phy(spi_phy, ififo_depth=4))
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
+        self.csr_devices.append("rtio_core")
+        if self.acpki:
+            import acpki
+
+            self.config["KI_IMPL"] = "acp"
+            self.config["ACPKI_BATCH_SIZE"] = int(acpki_batch_size)
+            self.submodules.rtio = acpki.KernelInitiator(
+                self.rtio_tsc,
+                bus=self.ps7.s_axi_acp,
+                user=self.ps7.s_axi_acp_user,
+                evento=self.ps7.event.o,
+            )
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri],
+            enable_routing=True,
+        )
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(
+            self.rtio_tsc, self.rtio_core.cri, self.ps7.s_axi_hp1
+        )
+        self.csr_devices.append("rtio_analyzer")
+
+
+class BASE(EBAZ4205):
+    def __init__(self, rtio_clk, acpki, acpki_batch_size):
+        EBAZ4205.__init__(self, rtio_clk, acpki, acpki_batch_size)
+
+
+VARIANTS = {cls.__name__.lower(): cls for cls in [BASE]}
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner"
+    )
+    parser.add_argument(
+        "-r", default=None, help="build Rust interface into the specified file"
+    )
+    parser.add_argument(
+        "-m", default=None, help="build Rust memory interface into the specified file"
+    )
+    parser.add_argument(
+        "-c",
+        default=None,
+        help="build Rust compiler configuration into the specified file",
+    )
+    parser.add_argument(
+        "-g", default=None, help="build gateware into the specified directory"
+    )
+    parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)")
+    parser.add_argument("--acpki-batch-size", default=10000, help="ACPKI batch buffer size")
+    parser.add_argument(
+        "-V",
+        "--variant",
+        default="base",
+        help="variant: " "[acpki_]base" "(default: %(default)s)",
+    )
+    args = parser.parse_args()
+
+    rtio_clk = int(args.rtio_clk)
+    variant = args.variant.lower()
+    acpki = variant.startswith("acpki_")
+    if acpki:
+        variant = variant[6:]
+
+    try:
+        cls = VARIANTS[variant]
+    except KeyError:
+        raise SystemExit("Invalid variant (-V/--variant)")
+
+    soc = cls(rtio_clk=rtio_clk, acpki=acpki, acpki_batch_size=args.acpki_batch_size)
+    soc.finalize()
+
+    if args.r is not None:
+        write_csr_file(soc, args.r)
+    if args.m is not None:
+        write_mem_file(soc, args.m)
+    if args.c is not None:
+        write_rustc_cfg_file(soc, args.c)
+    if args.g is not None:
+        soc.build(build_dir=args.g)
+
+
+if __name__ == "__main__":
+    main()

src/gateware/kasli_soc.py

@@ -0,0 +1,803 @@
+#!/usr/bin/env python
+
+import argparse
+
+from migen import *
+from migen.build.generic_platform import *
+from migen.genlib.cdc import MultiReg
+from migen_axi.integration.soc_core import SoCCore
+from migen_axi.platforms import kasli_soc
+from misoc.interconnect.csr import *
+from misoc.cores import virtual_leds
+
+from artiq.coredevice import jsondesc
+from artiq.gateware import rtio, eem_7series
+from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
+from artiq.gateware.rtio.phy import ttl_simple, cxp_grabber
+from artiq.gateware.drtio.transceiver import gtx_7series, eem_serdes
+from artiq.gateware.drtio.siphaser import SiPhaser7Series
+from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
+from artiq.gateware.drtio import *
+from artiq.gateware.wrpll import wrpll
+
+import dma
+import analyzer
+import acpki as acpki_lib
+import drtio_aux_controller
+import zynq_clocking
+from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
+
+eem_iostandard_dict = {
+     0: "LVDS_25",
+     1: "LVDS_25",
+     2: "LVDS",
+     3: "LVDS",
+     4: "LVDS",
+     5: "LVDS",
+     6: "LVDS",
+     7: "LVDS",
+     8: "LVDS_25",
+     9: "LVDS_25",
+    10: "LVDS",
+    11: "LVDS",
+}
+
+DRTIO_EEM_PERIPHERALS = ["shuttler", "phaser_drtio"]
+
+def eem_iostandard(eem):
+    return IOStandard(eem_iostandard_dict[eem])
+
+
+class SMAClkinForward(Module):
+    def __init__(self, platform):
+        sma_clkin = platform.request("sma_clkin")
+        sma_clkin_se = Signal()
+        cdr_clk_se = Signal()
+        cdr_clk = platform.request("cdr_clk")
+        self.specials += [
+            Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
+            Instance("ODDR", i_C=sma_clkin_se, i_CE=1, i_D1=1, i_D2=0, o_Q=cdr_clk_se),
+            Instance("OBUFDS", i_I=cdr_clk_se, o_O=cdr_clk.p, o_OB=cdr_clk.n)
+        ]
+
+
+class GTPBootstrapClock(Module):
+    def __init__(self, platform, freq=125e6):
+        self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
+        self.cd_bootstrap.clk.attr.add("keep")
+
+        bootstrap_125 = platform.request("clk125_gtp")
+        bootstrap_se = Signal()
+        clk_out = Signal()
+        platform.add_period_constraint(bootstrap_125.p, 8.0)
+        self.specials += [
+            Instance("IBUFDS_GTE2",
+                i_CEB=0,
+                i_I=bootstrap_125.p, i_IB=bootstrap_125.n, 
+                o_O=bootstrap_se,
+                p_CLKCM_CFG="TRUE",
+                p_CLKRCV_TRST="TRUE",
+                p_CLKSWING_CFG=3),
+            Instance("BUFG", i_I=bootstrap_se, o_O=clk_out)
+        ]
+        if freq == 125e6:
+            self.comb += self.cd_bootstrap.clk.eq(clk_out)
+        elif freq == 100e6:
+            pll_fb = Signal()
+            pll_out = Signal()
+            self.specials += [
+                Instance("PLLE2_BASE",
+                    p_CLKIN1_PERIOD=8.0,
+                    i_CLKIN1=clk_out,
+                    i_CLKFBIN=pll_fb,
+                    o_CLKFBOUT=pll_fb,
+
+                    # VCO @ 1GHz
+                    p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
+
+                    # 100MHz for bootstrap
+                    p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_out,
+                ),
+                Instance("BUFG", i_I=pll_out, o_O=self.cd_bootstrap.clk)
+            ]
+        else:
+            raise ValueError("Bootstrap frequency must be 100 or 125MHz")
+
+
+def add_coaxpress_sfp(cls, clk_freq, roi_engine_count, refclk=None):
+    if refclk is None:
+        refclk = Signal()
+        gt_refclk_pad = cls.platform.request("clk_gtp")
+        cls.platform.add_period_constraint(gt_refclk_pad.p, 8.0)
+        cls.specials += Instance("IBUFDS_GTE2",
+            i_CEB=0,
+            i_I=gt_refclk_pad.p,
+            i_IB=gt_refclk_pad.n,
+            o_O=refclk,
+            p_CLKCM_CFG="TRUE",
+            p_CLKRCV_TRST="TRUE",
+            p_CLKSWING_CFG=3
+        )
+
+    sfp_slot = 0
+    cls.submodules.cxp_grabber = cxp_grabber.CXPGrabber(
+        refclk=refclk,
+        gt_pads=[cls.platform.request("sfp", sfp_slot)],
+        sys_clk_freq=clk_freq,
+        roi_engine_count=roi_engine_count
+    )
+    cls.config["HAS_CXP_LED"] = None
+
+    mem_size = cls.cxp_grabber.core.get_mem_size()
+    # upper half is tx while lower half is rx
+    memory_address = cls.axi2csr.register_port(cls.cxp_grabber.core.get_tx_port(), mem_size)
+    cls.axi2csr.register_port(cls.cxp_grabber.core.get_rx_port(), mem_size)
+    cls.add_memory_region("cxp_mem", cls.mem_map["csr"] + memory_address, mem_size * 2)
+    cls.csr_devices.append("cxp_grabber")
+
+    print("CoaXPress-SFP (SFP{}) at RTIO channel 0x{:06x}".format(sfp_slot, len(cls.rtio_channels)))
+    cls.rtio_channels += [
+        rtio.Channel(cls.cxp_grabber.trigger),
+        rtio.Channel(cls.cxp_grabber.config),
+        rtio.Channel(cls.cxp_grabber.gate_data),
+    ]
+    # max freq of cxp_gt_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
+    rx = cls.cxp_grabber.phy.phys[0]
+    cls.platform.add_period_constraint(rx.gtx.cd_cxp_gt_rx.clk, 3.2)
+    # constraint the clk path 
+    cls.platform.add_false_path_constraints(cls.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gt_rx.clk)
+
+class GenericStandalone(SoCCore):
+    def __init__(self, description):
+        self.acpki = description["enable_acpki"]
+        clk_freq = description["rtio_frequency"]
+        with_wrpll = description["enable_wrpll"]
+
+        platform = kasli_soc.Platform()
+        platform.toolchain.bitstream_commands.extend([
+            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+        ])
+        ident = generate_ident(description["variant"])
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
+
+        self.config["HW_REV"] = description["hw_rev"]
+        clk_synth = platform.request("cdr_clk_clean_fabric")
+        clk_synth_se = Signal()
+        clk_synth_se_buf = Signal()
+        platform.add_period_constraint(clk_synth.p, 8.0)
+
+        self.specials += [ 
+            Instance("IBUFGDS",
+                p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
+                i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se
+            ),
+            Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf),
+        ]
+        fix_serdes_timing_path(platform)
+        self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
+        self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
+        self.config["CLOCK_FREQUENCY"] = int(clk_freq)
+
+        self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se_buf)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
+        self.csr_devices.append("sys_crg")
+        self.crg = self.ps7 # HACK for eem_7series to find the clock
+        self.crg.cd_sys = self.sys_crg.cd_sys
+
+        if with_wrpll:
+            self.submodules.wrpll_refclk = wrpll.FrequencyMultiplier(platform.request("sma_clkin"))
+            self.submodules.wrpll = wrpll.WRPLL(
+                platform=self.platform,
+                cd_ref=self.wrpll_refclk.cd_ref,
+                main_clk_se=clk_synth_se)
+            self.csr_devices.append("wrpll_refclk")
+            self.csr_devices.append("wrpll")
+            self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
+            self.config["HAS_SI549"] = None
+            self.config["WRPLL_REF_CLK"] = "SMA_CLKIN"
+        else:
+            self.submodules += SMAClkinForward(self.platform)
+            self.config["HAS_SI5324"] = None
+            self.config["SI5324_SOFT_RESET"] = None
+
+        self.rtio_channels = []
+
+        has_grabber = False
+        eem_peripherals = []
+        for peripheral in description["peripherals"]:
+            if peripheral["type"] == "coaxpress_sfp":
+                add_coaxpress_sfp(self, clk_freq, peripheral["roi_engine_count"])
+            elif peripheral["type"] == "grabber":
+                has_grabber = True
+                self.grabber_csr_group = []
+                eem_peripherals.append(peripheral)
+            else:
+                eem_peripherals.append(peripheral)
+        eem_7series.add_peripherals(self, eem_peripherals, iostandard=eem_iostandard)
+        for i in (0, 1):
+            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            user_led = self.platform.request("user_led", i)
+            phy = ttl_simple.Output(user_led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+        self.submodules.rtio_core = rtio.Core(
+            self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
+        )
+        self.csr_devices.append("rtio_core")
+
+        if self.acpki:
+            self.config["KI_IMPL"] = "acp"
+            self.config["ACPKI_BUFFER_SIZE"] = int(description["acpki_buffer_size"])
+            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
+                                                             bus=self.ps7.s_axi_acp,
+                                                             user=self.ps7.s_axi_acp_user,
+                                                             evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri])
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+        if has_grabber:
+            self.config["HAS_GRABBER"] = None
+            self.add_csr_group("grabber", self.grabber_csr_group)
+            for grabber in self.grabber_csr_group:
+                self.platform.add_false_path_constraints(
+                    self.sys_crg.cd_sys.clk, getattr(self, grabber).deserializer.cd_cl.clk)
+
+
+class GenericMaster(SoCCore):
+    def __init__(self, description):
+        clk_freq = description["rtio_frequency"]
+        with_wrpll = description["enable_wrpll"]
+
+        has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
+        self.acpki = description["enable_acpki"]
+
+        platform = kasli_soc.Platform()
+        platform.toolchain.bitstream_commands.extend([
+            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+        ])
+        ident = generate_ident(description["variant"])
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
+
+        self.config["HW_REV"] = description["hw_rev"]
+
+        eem_peripherals = []
+        drtio_sfp_slots = list(range(4))
+        has_coaxpress_sfp, has_grabber = False, False
+        for peripheral in description["peripherals"]:
+            if peripheral["type"] == "coaxpress_sfp":
+                has_coaxpress_sfp = True
+                cxp_roi_counts = peripheral["roi_engine_count"]
+                # use sfp slot 0 for coaxpress_sfp
+                drtio_sfp_slots = list(range(1, 4))
+            elif peripheral["type"] == "grabber":
+                has_grabber = True
+                eem_peripherals.append(peripheral)
+            else:
+                eem_peripherals.append(peripheral)
+
+        self.submodules.gt_drtio = gtx_7series.GTX(
+            clock_pads=platform.request("clk_gtp"),
+            pads=[self.platform.request("sfp", i) for i in drtio_sfp_slots],
+            clk_freq=clk_freq)
+        self.csr_devices.append("gt_drtio")
+        self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
+        self.config["CLOCK_FREQUENCY"] = int(clk_freq)
+
+        txout_buf = Signal()
+        gtx0 = self.gt_drtio.gtxs[0]
+        self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
+
+        ext_async_rst = Signal()
+
+        self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
+        self.submodules.sys_crg = zynq_clocking.SYSCRG(
+            self.platform,
+            self.ps7,
+            txout_buf,
+            clk_sw=self.gt_drtio.stable_clkin.storage,
+            clk_sw_status=gtx0.tx_init.done,
+            ext_async_rst=ext_async_rst)
+        self.csr_devices.append("sys_crg")
+        self.crg = self.ps7 # HACK for eem_7series to find the clock
+        self.crg.cd_sys = self.sys_crg.cd_sys
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
+        fix_serdes_timing_path(platform)
+
+        self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
+        self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
+
+        if with_wrpll:
+            clk_synth = platform.request("cdr_clk_clean_fabric")
+            clk_synth_se = Signal()
+            platform.add_period_constraint(clk_synth.p, 8.0)
+            self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
+            self.submodules.wrpll_refclk = wrpll.FrequencyMultiplier(platform.request("sma_clkin"))
+            self.submodules.wrpll = wrpll.WRPLL(
+                platform=self.platform,
+                cd_ref=self.wrpll_refclk.cd_ref,
+                main_clk_se=clk_synth_se)
+            self.csr_devices.append("wrpll_refclk")
+            self.csr_devices.append("wrpll")
+            self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
+            self.config["HAS_SI549"] = None