af99a06919
allow toggling SED spread with flash config key
2024-07-09 10:32:01 +02:00
c2d645ed0a
enable spread in satellite, use high watermark
2024-05-23 17:18:16 +08:00
b6ac052e9f
aux_controller: multiple receiver buffers
2024-04-25 10:46:57 +08:00
76d704ac33
drtio: revert async flag message
2024-04-25 10:46:57 +08:00
1cc7398bc0
drtio: add sat -> mst async notif packet
2024-01-09 08:44:45 +08:00
9f4b8db2de
repeater: fix setting tsc
2023-12-01 16:43:48 +08:00
8f7d138dbd
gtx: Always enable IBUFDS_GTE2, add clk_path_ready
...
- Set clk_path_ready to High to start Initialization of GTP TX and RX
2023-11-07 18:36:48 +08:00
bb0b8a6c00
kasli: Correct the GTP TX clock path during init
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- TXOUT must be fed back into TXUSRCLK during initialization
- Now, MMCM Clock Input is switched before GTP TX Init is started instead of after GTP TX Init is done
- Reset in Sys Clock domain is kept asserted when clock is switched and GTP TX Init is NOT done
2023-11-07 13:40:32 +08:00
occheung
b52f253dbd
Simplify OOB reset by clock division ( #2217 )
...
* oob: simply logic by dividing into clk100
* replace clk100 clk ctrl with clk200 async reset
* fix comment (singular/plural)
* oob reset: invoke platform commands locally
* cleanup
* oob reset: add async reset import
* fix duplicated comment
2023-09-26 08:02:49 +08:00
7f63bb322d
disable DRTIO-over-EEM OSERDES until clock is stable
...
This asserts OOB reset on EFC.
2023-09-05 16:59:01 +08:00
occheung
838cc80922
EFC: Implement OOB reset
2023-09-03 10:25:08 +08:00
5d38db19d0
drtio-eem: remove unnecessary rtio_rx clock domain
2023-08-25 11:32:28 +08:00
occheung
64d3f867a0
add DRTIO-over-EEM PHY
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for EFC and perhaps Phaser
2023-08-09 23:59:40 +00:00
48bc8a2ecc
gtx_7series_init: GTH -> GTX (NFC)
2023-07-10 11:26:07 +08:00
93882eb3ce
kasli-soc: fix of SYS CLK switch failure
...
Change initialization behaviour of GTX transceivers
--
Modify the config parms CPLL of GTX transceiver for PLL to lock correctly
Modify the enabling requirement of GTX input clock buffer IBUFDS_GTE2 so
that it depends on GTX PLL locked signal instead of TX Init Done
Modify the GTX Init FSM so that BruteForceClock Aligner can reset GTX
transceiver without resetting the GTX transceiver PLL
kasli-soc: fix of SYS CLK switch failure
Changed initialization of GTX transceivers.
Successful SYS CLK switching requires IBUFDS_GTE2 to be properly enabled and not disabled during GTX transceiver initialization.
For this reason, CPLL is not reset during GTX initialization and clock alignment.
kasli-soc: refractor fix of SYS CLK switch failure
Remove gtXxreset & cpllreset assertion and deassertion
The removed code does not affect the fix
2023-07-10 03:24:28 +00:00
22e2514ce6
update configuration of IBUFDS_GTE2
...
Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
2023-05-30 11:42:51 +08:00
70edc9c5c6
test_write_underflow: decrease underflow delay
2023-01-11 12:02:51 +08:00
ec893222a4
rtio: remove support for async mode
2023-01-06 18:22:05 +08:00
cf2a4972f7
remove WRPLL
2023-01-06 17:53:11 +08:00
5da9794895
remove Sayma and Metlino support
2023-01-06 17:41:12 +08:00
3838dfc1d1
DRTIO: RTIO/SYS clock merge, KC705
2023-01-06 07:13:38 +08:00
17efc28dbe
DRTIO: RTIO/SYS clock merge
2022-12-17 15:39:54 +08:00
Alex Wong Tat Hang
a3ae82502c
gtx_7series: fix IBUFGS_GTE2 buffer parameters
...
Co-authored-by: topquark12 <aw@m-labs.hk>
2022-08-01 10:21:28 +08:00
f281112779
satman: add 100mhz si5324 settings
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siphaser: add calculated vco for 100mhz comment
2021-12-03 17:19:11 +08:00
eec3ea6589
siphaser: add support for 100mhz rtio
2021-12-03 17:19:11 +08:00
c6e0e26440
drtio: accept 32b/64b bus
2021-11-08 16:59:08 +08:00
7879d3630b
made kc705/gtx interface more similar to kasli/gtp
2021-08-10 18:53:52 +08:00
a0fd5261ea
kc705: cleanup
2021-01-22 11:11:13 +08:00
88b14082b6
drtio/transceiver/gtx: delete obsolete modules
2021-01-20 15:05:32 +08:00
52afd4ef6b
kc705: add GTX multilane support, add multichannel support on master
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* One DRTIO master channel is enabled by default.
* User can set the SMA as the 2nd master channel (by passing --drtio-sma to the argparser).
* Multi-channel (i.e. with repeaters) on KC705 satellite is supported but has not been implemented yet.
2021-01-20 15:05:32 +08:00
f25e86e934
kc705: revive DRTIO satellite with updated syntax, update GTX
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* Multi-channel has not been implemented yet.
2021-01-20 11:25:38 +08:00
cff7bcc122
Merge branch 'master' ( 43be383c86) into k7-drtio
2020-12-31 13:30:46 +08:00
dc7addf394
Revert "drtio: remove KC705/GTX support"
...
This reverts commit ebdbaaad32
2020-12-31 13:29:50 +08:00
ea95d91428
wrpll: separate collector reset
2020-11-09 17:57:13 +08:00
d185f1ac67
wrpll: fix mulshift (2)
2020-10-17 00:32:02 +08:00
3f076bf79b
wrpll: fix mulshift
2020-10-16 22:05:37 +08:00
db62cf2abe
wrpll: convert tests to self-checking unittests
2020-10-08 18:38:01 +08:00
07d43b6e5f
wrpll: babysit Vivado DSP retiming
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Design now passes timing.
2020-10-08 17:51:27 +08:00
6248970ef8
wrpll: clean up matlab comparison test
2020-10-08 15:40:15 +08:00
hartytp
cd8c2ce713
wrpll: add test to compare collector+filter against Matlab simulation
2020-10-08 15:36:56 +08:00
hartytp
d780faf4ac
wrpll.si549: initialize the clock divider to a sensible value
2020-10-08 15:32:27 +08:00
hartytp
7d7be6e711
wrpll.core: move collector into helper CD so we can get tags out while the filters are reset
2020-10-08 15:32:27 +08:00
3fa5d0b963
wrpll: clean up sign extension
2020-10-08 15:32:27 +08:00
hartytp
87911810d6
wrpll.core: add CSRs to monitor the collector outputs
2020-10-08 15:32:27 +08:00
hartytp
f2f942a8b4
wrpll.ddmtd: remove CSRs from DDMTD
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We will gather then from the collector output so we can get all tags on the same cycle
2020-10-08 15:32:27 +08:00
hartytp
85bb641917
wrpll.ddmtd: fix first edge deglitcher
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The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
2020-10-08 15:32:27 +08:00
hartytp
f3cd0fc675
wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit.
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TODO: think about this and pick a sensible threshold (and also think about integrator anti windup)
2020-10-08 15:32:27 +08:00
hartytp
e5e648bde1
wrpll: add bit shift for collector helper output
2020-10-08 15:32:27 +08:00
hartytp
c9ae406ac6
wrpll: change the DDMTD helper frequency to match CERN, improve docs
2020-10-08 15:32:27 +08:00
hartytp
f6f6045f1a
wrpll.thls: fix make
2020-10-08 15:32:27 +08:00
