forked from M-Labs/artiq
gtx: Always enable IBUFDS_GTE2, add clk_path_ready
- Set clk_path_ready to High to start Initialization of GTP TX and RX
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@ -279,14 +279,13 @@ class GTX(Module, TransceiverInterface):
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self.nchannels = nchannels = len(pads)
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self.gtxs = []
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self.rtio_clk_freq = clk_freq
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self.clk_path_ready = Signal()
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# # #
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refclk = Signal()
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clk_enable = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=~clk_enable,
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i_CEB=0,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk,
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@ -315,14 +314,10 @@ class GTX(Module, TransceiverInterface):
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for n, gtx in enumerate(self.gtxs):
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self.comb += [
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gtx.txenable.eq(self.txenable.storage[n]),
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gtx.tx_init.stable_clkin.eq(clk_enable)
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gtx.tx_init.clk_path_ready.eq(self.clk_path_ready)
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]
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# rx_init is in SYS domain, rather than bootstrap
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self.specials += MultiReg(clk_enable, gtx.rx_init.stable_clkin)
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# stable_clkin resets after reboot since it's in SYS domain
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# still need to keep clk_enable high after this
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self.sync.bootstrap += clk_enable.eq(self.stable_clkin.storage | self.gtxs[0].tx_init.cplllock)
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self.specials += MultiReg(self.clk_path_ready, gtx.rx_init.clk_path_ready)
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# Connect slave i's `rtio_rx` clock to `rtio_rxi` clock
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for i in range(nchannels):
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@ -16,7 +16,7 @@ class GTXInit(Module):
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assert mode in ["single", "master", "slave"]
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self.mode = mode
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self.stable_clkin = Signal()
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self.clk_path_ready = Signal()
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self.done = Signal()
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self.restart = Signal()
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@ -110,7 +110,7 @@ class GTXInit(Module):
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startup_fsm.act("INITIAL",
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startup_timer.wait.eq(1),
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If(startup_timer.done & self.stable_clkin, NextState("RESET_PLL"))
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If(startup_timer.done & self.clk_path_ready, NextState("RESET_PLL"))
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)
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startup_fsm.act("RESET_PLL",
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gtXxreset.eq(1),
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