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drtio-eem: remove unnecessary rtio_rx clock domain

This commit is contained in:
Sebastien Bourdeauducq 2023-08-25 11:32:28 +08:00
parent 9bee4b9697
commit 5d38db19d0
4 changed files with 15 additions and 15 deletions

View File

@ -27,12 +27,13 @@ class ChannelInterface:
class TransceiverInterface(AutoCSR):
def __init__(self, channel_interfaces):
def __init__(self, channel_interfaces, *, async_rx=True):
self.stable_clkin = CSRStorage()
self.txenable = CSRStorage(len(channel_interfaces))
for i in range(len(channel_interfaces)):
name = "rtio_rx" + str(i)
setattr(self.clock_domains, "cd_"+name, ClockDomain(name=name))
if async_rx:
for i in range(len(channel_interfaces)):
name = "rtio_rx" + str(i)
setattr(self.clock_domains, "cd_"+name, ClockDomain(name=name))
self.channels = channel_interfaces

View File

@ -2,6 +2,12 @@ from migen import *
from migen.genlib.cdc import ElasticBuffer
class NoRXSynchronizer:
"""To be used when RX is already synchronous (e.g. IOSERDES based PHY)."""
def resync(self, signal):
return signal
class GenericRXSynchronizer(Module):
"""Simple RX synchronizer based on the portable Migen elastic buffer.

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@ -472,10 +472,4 @@ class EEMSerdes(Module, TransceiverInterface, AutoCSR):
self.submodules += serdes_list
TransceiverInterface.__init__(self, channel_interfaces)
for i in range(len(serdes_list)):
self.comb += [
getattr(self, "cd_rtio_rx" + str(i)).clk.eq(ClockSignal()),
getattr(self, "cd_rtio_rx" + str(i)).rst.eq(ResetSignal())
]
TransceiverInterface.__init__(self, channel_interfaces, async_rx=False)

View File

@ -14,7 +14,7 @@ from artiq.gateware import rtio
from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
from artiq.gateware.rtio.phy import ttl_simple
from artiq.gateware.drtio.transceiver import eem_serdes
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
from artiq.gateware.drtio.rx_synchronizer import NoRXSynchronizer
from artiq.gateware.drtio import *
from artiq.build_soc import *
@ -69,11 +69,10 @@ class Satellite(BaseSoC, AMPSoC):
self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
cdr = ClockDomainsRenamer({"rtio_rx": "sys"})
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.eem_transceiver.channels[0],
self.rx_synchronizer))
NoRXSynchronizer()))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")