forked from M-Labs/artiq
EFC: Implement OOB reset
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904afe1632
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838cc80922
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@ -11,6 +11,7 @@ class RXSerdes(Module):
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self.cnt_in = [ Signal(5) for _ in range(4) ]
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self.cnt_out = [ Signal(5) for _ in range(4) ]
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self.bitslip = [ Signal() for _ in range(4) ]
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self.o = [ Signal() for _ in range(4) ]
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ser_in_no_dly = [ Signal() for _ in range(4) ]
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ser_in = [ Signal() for _ in range(4) ]
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@ -34,6 +35,7 @@ class RXSerdes(Module):
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o_Q6=self.rxdata[i][4],
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o_Q7=self.rxdata[i][3],
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o_Q8=self.rxdata[i][2],
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o_O=self.o[i],
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o_SHIFTOUT1=shifts[i][0],
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o_SHIFTOUT2=shifts[i][1],
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i_DDLY=ser_in[i],
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@ -391,6 +393,56 @@ class SerdesSingle(Module):
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& decoders[0].k))
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class OOBReset(Module):
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def __init__(self, iserdes_o):
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ce_counter = Signal(13)
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activity_ce = Signal()
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transition_ce = Signal()
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self.sync.clk200 += Cat(ce_counter, activity_ce).eq(ce_counter + 1)
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self.comb += transition_ce.eq(ce_counter[0])
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idle_low_meta = Signal()
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idle_high_meta = Signal()
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idle_low = Signal()
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idle_high = Signal()
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idle = Signal()
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self.rst = Signal(reset=1)
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# Detect the lack of transitions (idle) within 2 clk200 cycles
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self.specials += [
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Instance("FDCE", p_INIT=1, i_D=1, i_CLR=iserdes_o,
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i_CE=transition_ce, i_C=ClockSignal("clk200"), o_Q=idle_low_meta,
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attr={"async_reg", "ars_ff1"}),
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Instance("FDCE", p_INIT=1, i_D=idle_low_meta, i_CLR=0,
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i_CE=transition_ce, i_C=ClockSignal("clk200"), o_Q=idle_low,
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attr={"async_reg", "ars_ff2"}),
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Instance("FDCE", p_INIT=1, i_D=1, i_CLR=~iserdes_o,
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i_CE=transition_ce, i_C=ClockSignal("clk200"), o_Q=idle_high_meta,
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attr={"async_reg", "ars_ff1"}),
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Instance("FDCE", p_INIT=1, i_D=idle_high_meta, i_CLR=0,
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i_CE=transition_ce, i_C=ClockSignal("clk200"), o_Q=idle_high,
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attr={"async_reg", "ars_ff2"}),
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]
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# Detect activity for the last 2**13 clk200 cycles
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# The 2**13 cycles are fully partitioned into 2**12 time segments of 2
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# cycles in duration. If there exists 2-cycle time segment without
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# signal level transition, rst is asserted.
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self.sync.clk200 += [
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If(activity_ce,
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idle.eq(0),
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self.rst.eq(idle),
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),
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If(idle_low | idle_high,
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idle.eq(1),
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self.rst.eq(1),
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),
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]
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class EEMSerdes(Module, TransceiverInterface, AutoCSR):
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def __init__(self, platform, data_pads):
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self.rx_ready = CSRStorage()
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@ -472,4 +524,8 @@ class EEMSerdes(Module, TransceiverInterface, AutoCSR):
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self.submodules += serdes_list
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self.submodules.oob_reset = OOBReset(serdes_list[0].rx_serdes.o[0])
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self.rst = self.oob_reset.rst
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self.rst.attr.add("no_retiming")
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TransceiverInterface.__init__(self, channel_interfaces, async_rx=False)
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@ -89,6 +89,9 @@ class Satellite(BaseSoC, AMPSoC):
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self.add_csr_group("drtioaux", ["drtioaux0"])
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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# Async reset gateware if data lane is idle
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self.comb += self.crg.reset.eq(self.eem_transceiver.rst)
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i2c = self.platform.request("fpga_i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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