forked from M-Labs/artiq
update configuration of IBUFDS_GTE2
Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
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parent
a4895b591a
commit
22e2514ce6
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@ -288,9 +288,9 @@ class GTX(Module, TransceiverInterface):
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk,
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p_CLKCM_CFG="0b1",
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p_CLKRCV_TRST="0b1",
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p_CLKSWING_CFG="0b11"
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p_CLKCM_CFG="TRUE",
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p_CLKRCV_TRST="TRUE",
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p_CLKSWING_CFG=3
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)
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channel_interfaces = []
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@ -87,7 +87,10 @@ class StandaloneBase(MiniSoC, AMPSoC):
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Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=cdr_clk_out.p, i_IB=cdr_clk_out.n,
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o_O=cdr_clk),
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o_O=cdr_clk,
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p_CLKCM_CFG="TRUE",
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p_CLKRCV_TRST="TRUE",
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p_CLKSWING_CFG=3),
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Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
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]
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@ -378,7 +381,10 @@ class MasterBase(MiniSoC, AMPSoC):
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=cdr_clk_out.p, i_IB=cdr_clk_out.n,
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o_O=cdr_clk)
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o_O=cdr_clk,
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p_CLKCM_CFG="TRUE",
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p_CLKRCV_TRST="TRUE",
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p_CLKSWING_CFG=3)
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# Note precisely the rules Xilinx made up:
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# refclksel=0b001 GTREFCLK0 selected
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# refclksel=0b010 GTREFCLK1 selected
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@ -440,7 +446,10 @@ class SatelliteBase(BaseSoC):
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=cdr_clk_out.p, i_IB=cdr_clk_out.n,
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o_O=cdr_clk)
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o_O=cdr_clk,
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p_CLKCM_CFG="TRUE",
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p_CLKRCV_TRST="TRUE",
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p_CLKSWING_CFG=3)
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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@ -119,9 +119,9 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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i_CEB=0,
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i_I=cdr_clk_out.p, i_IB=cdr_clk_out.n,
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o_O=cdr_clk,
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p_CLKCM_CFG=1,
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p_CLKRCV_TRST=1,
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p_CLKSWING_CFG="2'b11"),
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p_CLKCM_CFG="TRUE",
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p_CLKRCV_TRST="TRUE",
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p_CLKSWING_CFG=3),
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Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
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]
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