b5c035bb52
sayma_rtm: constrain serwb clock input
2018-01-23 13:54:53 +00:00
aada38f508
kasli, kc705: remove vivado "keep", cleanup a constraint
2018-01-23 13:15:26 +00:00
85102e191e
sayma_rtm: derive clocks automatically
...
* also don't add false paths unless necessary
2018-01-23 11:00:55 +00:00
7d1b3f37c9
sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress
2018-01-23 10:56:42 +00:00
649deccd9b
kasli: fix DRTIO satellite QPLL refclksel
2018-01-23 12:27:19 +08:00
4b4374f76a
sayma: register_jref for JESD204. Closes #904
2018-01-23 12:19:15 +08:00
763aefacff
kasli: fix typo
2018-01-23 12:10:54 +08:00
c7b148a704
kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1
2018-01-23 12:08:10 +08:00
d6157514c7
gtp_7series: flexible QPLL channel selection
2018-01-23 12:03:09 +08:00
9f87c34a94
kasli: fix QPLL instantiation
2018-01-23 10:39:31 +08:00
98a5607634
gtp_7series: set clock muxes correctly for second QPLL channel
2018-01-23 10:39:20 +08:00
25fee1a0bb
gtp_7series: use QPLL second channel
2018-01-23 10:15:49 +08:00
031d7ff020
kasli: keep using second QPLL channel for DRTIO satellite
2018-01-23 10:13:10 +08:00
626075cbc1
gtp_7series: simplify TX clocking
2018-01-23 09:49:23 +08:00
401e57d41c
gtp_7series: fix nchannels assert
2018-01-23 01:28:01 +08:00
aa62e91487
kasli: add DRTIO targets (no firmware)
2018-01-23 01:27:40 +08:00
296ac35f5d
sayma_amc: SFP TX disable is active-high
2018-01-23 00:32:09 +08:00
77192256ea
kc705: style
2018-01-23 00:02:35 +08:00
ab7c49d6d0
sayma_amc: raise error on invalid variant
2018-01-23 00:02:16 +08:00
c1ac3b66b1
sayma_rtm: fix 8fe463d4a
2018-01-23 00:01:45 +08:00
53facfef13
sayma: build fixes
2018-01-22 18:33:22 +08:00
25f3feeda8
refactor targets
2018-01-22 18:25:10 +08:00
5198c224a2
sayma,kasli: use new pin names
2018-01-22 11:51:07 +08:00
Florent Kermarrec
8fe463d4a0
sayma_rtm: add UART loopback to easily know if rtm fpga is alive
2018-01-20 06:04:34 +01:00
Florent Kermarrec
74ce7319d3
sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?)
2018-01-20 06:04:18 +01:00
Florent Kermarrec
d27727968c
add artix7 gtp (3gbps), share clock aligner with gth_ultrascale
2018-01-19 12:17:54 +01:00
cdbf95d46a
kasli: fix permissions
2018-01-19 18:31:20 +08:00
8ec33ae7bd
kasli: feed EEM clock fan-out from SI5324
2018-01-17 17:27:59 +01:00
ed3e3b2791
sayma_amc: clarify --with-sawg help
2018-01-17 12:10:30 +01:00
Florent Kermarrec
f54b27b79c
sayma_amc: prepare for jesd subclass 1
2018-01-17 11:49:36 +01:00
Florent Kermarrec
f73c3e5944
gateware/test/serwb: update and cleanup test (v2...)
2018-01-16 20:06:43 +01:00
7405006668
sayma: rtio clock is jesd fabric clock
2018-01-16 18:19:04 +01:00
whitequark
247167d34a
Revert "gateware/test/serwb: update and cleanup tests"
...
This reverts commit 5b03cc2fae
2018-01-16 08:21:26 +00:00
whitequark
444b901dbe
sayma: add RTM configuration port.
2018-01-16 07:28:00 +00:00
Florent Kermarrec
5b03cc2fae
gateware/test/serwb: update and cleanup tests
2018-01-15 21:53:40 +01:00
whitequark
6891141fa6
artiq_flash: add sayma support.
2018-01-15 11:43:29 +00:00
529033e016
kernel_cpu: disable PCU
...
* contributes to long timing paths on artix 7 (kasli)
* currently only used for testing and debugging
2018-01-12 12:03:50 +00:00
ac3c3871d0
kasli: s/extensions/variant/g
2018-01-12 12:29:42 +01:00
7c82fcf41a
targets: avoid passing cpu_type around unnecessarily
2018-01-11 11:21:55 +08:00
6d58c4390b
Merge branch 'sed-merge'
2018-01-10 13:14:39 +08:00
04b2fd3e13
sayma: fix AD9154NoSAWG ramp clock domain
2018-01-10 12:11:33 +08:00
dc593ec0f0
Merge branch 'rtio-sed' into sed-merge
2018-01-10 12:04:54 +08:00
Florent Kermarrec
2009734b3c
serwb/phy: get 625Mbps linerate working, increase timeout
2018-01-09 18:54:52 +01:00
Florent Kermarrec
9c6a7f7509
serwb/kusphy: use same serwb_serdes_5x reset than s7phy
2018-01-09 18:54:05 +01:00
8813aee6b1
targets: add kasli [wip, untested]
2018-01-04 16:12:12 +01:00
Florent Kermarrec
1e972034e8
gateware/targets: enable serwb scrambling on sayma amc & rtm
2018-01-03 17:34:46 +01:00
Florent Kermarrec
907af25a69
gateware/serwb: add scrambling, reduce cdc fifo depth
2018-01-03 17:34:03 +01:00
Florent Kermarrec
7f4756a869
gateware/serwb: cleanup packet
2018-01-03 17:30:12 +01:00
c2be820e9a
kc705_dds: make ext_clkout 100 MHz
2018-01-02 19:58:47 +01:00
43686f324b
kc705_dds: fix HPC voltages
...
* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V
* the direction control register on HPC (FMC-DIO to VHDCI)
was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
and hope for the best.
2018-01-02 13:41:07 +01:00
