forked from M-Labs/artiq
kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1
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d6157514c7
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c7b148a704
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@ -275,20 +275,24 @@ class Master(MiniSoC, AMPSoC):
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i_CEB=0,
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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qpll_eth_settings = QPLLSettings(
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# Note precisely the rules Xilinx made up:
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# refclksel=0b001 GTREFCLK0 selected
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# refclksel=0b010 GTREFCLK1 selected
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# but if only one clock used, then it must be 001.
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll_drtio_settings = QPLLSettings(
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qpll_eth_settings = QPLLSettings(
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refclksel=0b010,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(self.crg.clk125_buf, qpll_eth_settings,
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si5324_clkout_buf, qpll_drtio_settings)
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings
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self.crg.clk125_buf, qpll_eth_settings)
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self.submodules += qpll
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self.ethphy_qpll_channel, self.drtio_qpll_channel = qpll.channels
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self.drtio_qpll_channel, self.ethphy_qpll_channel = qpll.channels
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class Satellite(BaseSoC):
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@ -330,12 +334,12 @@ class Satellite(BaseSoC):
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(0, None, si5324_clkout_buf, qpll_drtio_settings)
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
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self.submodules += qpll
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self.comb += platform.request("sfp_ctl", 0).tx_disable.eq(0)
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self.submodules.transceiver = gtp_7series.GTP(
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qpll_channel=qpll.channels[1],
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qpll_channel=qpll.channels[0],
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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