forked from M-Labs/artiq
kc705: style
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@ -204,7 +204,7 @@ _urukul = [
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]
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class _Standalone_Base(MiniSoC, AMPSoC):
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class _StandaloneBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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@ -276,12 +276,12 @@ class _Standalone_Base(MiniSoC, AMPSoC):
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self.csr_devices.append("rtio_analyzer")
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class NIST_CLOCK(_Standalone_Base):
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class NIST_CLOCK(_StandaloneBase):
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"""
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NIST clock hardware, with old backplane and 11 DDS channels
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"""
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def __init__(self, **kwargs):
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_Standalone_Base.__init__(self, **kwargs)
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_StandaloneBase.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_clock.fmc_adapter_io)
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@ -377,13 +377,13 @@ class NIST_CLOCK(_Standalone_Base):
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self.add_rtio(rtio_channels)
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class NIST_QC2(_Standalone_Base):
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class NIST_QC2(_StandaloneBase):
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"""
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 24 DDS channels. Two backplanes are used.
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"""
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def __init__(self, **kwargs):
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_Standalone_Base.__init__(self, **kwargs)
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_StandaloneBase.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_qc2.fmc_adapter_io)
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@ -457,12 +457,12 @@ _sma_spi = [
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]
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class SMA_SPI(_Standalone_Base):
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class SMA_SPI(_StandaloneBase):
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"""
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SPI on 4 SMA for PDQ2 test/demo.
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"""
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def __init__(self, **kwargs):
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_Standalone_Base.__init__(self, **kwargs)
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_StandaloneBase.__init__(self, **kwargs)
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platform = self.platform
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self.platform.add_extension(_sma_spi)
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