forked from M-Labs/artiq
targets: add kasli [wip, untested]
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161a414567
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.build.generic_platform import *
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from migen.build.xilinx.vivado import XilinxVivadoToolchain
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from migen.build.xilinx.ise import XilinxISEToolchain
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.targets.kasli import (MiniSoC, soc_kasli_args,
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soc_kasli_argdict)
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi
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from artiq import __version__ as artiq_version
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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rtio_external_clk = Signal()
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clk_fpgaio_se = Signal()
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clk_fpgaio = platform.request("clk_fpgaio") # from Si5324
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platform.add_period_constraint(clk_fpgaio.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
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i_I=clk_fpgaio.p, i_IB=clk_fpgaio.n, o_O=clk_fpgaio_se),
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Instance("BUFG", i_I=clk_fpgaio_se, o_O=rtio_external_clk),
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]
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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]
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class _KasliBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, cpu_type="or1k", **kwargs):
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MiniSoC.__init__(self,
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cpu_type=cpu_type,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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self.submodules.leds = gpio.GPIOOut(Cat(
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self.platform.request("user_led", 0)))
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self.csr_devices.append("leds")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.rtio_crg.cd_rtio.clk.attr.add("keep")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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def _eem_signal(i):
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n = "d{}".format(i)
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if i == 0:
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n += "_cc"
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return n
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def _dio(eem):
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return [(eem, i,
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Subsignal("p", Pins("{}:{}_p".format(eem, _eem_signal(i)))),
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Subsignal("n", Pins("{}:{}_n".format(eem, _eem_signal(i)))),
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IOStandard("LVDS_25"))
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for i in range(8)]
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class Opticlock(_KasliBase):
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"""
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Opticlock extension configuration
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_KasliBase.__init__(self, cpu_type, **kwargs)
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platform = self.platform
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platform.add_extension(_dio("eem0"))
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platform.add_extension(_dio("eem1"))
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platform.add_extension(_dio("eem2"))
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# platform.add_extension(_urukul("eem3", "eem4"))
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# platform.add_extension(_novogorny("eem5"))
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rtio_channels = []
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for eem in "eem0 eem1 eem2".split():
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for i in range(8):
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phy = ttl_serdes_7series.Output_8X(
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platform.request(eem, i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in (1, 2):
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sfp = platform.request("sfp", i)
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phy = ttl_simple.Output(sfp.led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for Kasli systems")
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builder_args(parser)
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soc_kasli_args(parser)
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parser.add_argument("-E", "--extensions", default="opticlock",
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help="extension setup: opticlock "
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"(default: %(default)s)")
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args = parser.parse_args()
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extensions = args.extensions.lower()
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if extensions == "opticlock":
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cls = Opticlock
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else:
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raise SystemExit("Invalid hardware adapter string (-E/--extensions)")
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soc = cls(**soc_kasli_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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