forked from M-Labs/artiq
Revert "gateware/test/serwb: update and cleanup tests"
This reverts commit 5b03cc2fae.
This commit is contained in:
whitequark
parent
44cd7dfa23
commit
247167d34a
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@ -0,0 +1,70 @@
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import unittest
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import random
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from migen import *
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from misoc.interconnect.wishbone import SRAM
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from misoc.interconnect.stream import Converter
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from artiq.gateware.serwb import packet
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from artiq.gateware.serwb import etherbone
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class DUT(Module):
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def __init__(self):
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# wishbone slave
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slave_depacketizer = packet.Depacketizer(int(100e6))
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slave_packetizer = packet.Packetizer()
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self.submodules += slave_depacketizer, slave_packetizer
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slave_etherbone = etherbone.Etherbone(mode="slave")
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self.submodules += slave_etherbone
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self.comb += [
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slave_depacketizer.source.connect(slave_etherbone.sink),
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slave_etherbone.source.connect(slave_packetizer.sink)
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]
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# wishbone master
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master_depacketizer = packet.Depacketizer(int(100e6))
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master_packetizer = packet.Packetizer()
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self.submodules += master_depacketizer, master_packetizer
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master_etherbone = etherbone.Etherbone(mode="master")
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master_sram = SRAM(64, bus=master_etherbone.wishbone.bus)
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self.submodules += master_etherbone, master_sram
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self.comb += [
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master_depacketizer.source.connect(master_etherbone.sink),
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master_etherbone.source.connect(master_packetizer.sink)
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]
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# connect core directly with converters in the loop
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s2m_downconverter = Converter(32, 16)
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s2m_upconverter = Converter(16, 32)
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self.submodules += s2m_downconverter, s2m_upconverter
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m2s_downconverter = Converter(32, 16)
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m2s_upconverter = Converter(16, 32)
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self.submodules += m2s_upconverter, m2s_downconverter
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self.comb += [
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slave_packetizer.source.connect(s2m_downconverter.sink),
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s2m_downconverter.source.connect(s2m_upconverter.sink),
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s2m_upconverter.source.connect(master_depacketizer.sink),
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master_packetizer.source.connect(m2s_downconverter.sink),
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m2s_downconverter.source.connect(m2s_upconverter.sink),
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m2s_upconverter.source.connect(slave_depacketizer.sink)
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]
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# expose wishbone slave
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self.wishbone = slave_etherbone.wishbone.bus
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class TestEtherbone(unittest.TestCase):
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def test_write_read_sram(self):
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dut = DUT()
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prng = random.Random(1)
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def generator(dut):
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datas = [prng.randrange(0, 2**32-1) for i in range(16)]
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for i in range(16):
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yield from dut.wishbone.write(i, datas[i])
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for i in range(16):
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data = (yield from dut.wishbone.read(i))
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self.assertEqual(data, datas[i])
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run_simulation(dut, generator(dut))
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@ -1,128 +0,0 @@
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import unittest
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import random
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from migen import *
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from artiq.gateware.serwb import scrambler
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from artiq.gateware.serwb import SERWBCore
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from misoc.interconnect.wishbone import SRAM
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class FakeInit(Module):
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def __init__(self):
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self.ready = 1
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class FakeSerdes(Module):
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def __init__(self):
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self.tx_k = Signal(4)
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self.tx_d = Signal(32)
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self.rx_k = Signal(4)
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self.rx_d = Signal(32)
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class FakePHY(Module):
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cd = "sys"
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def __init__(self):
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self.init = FakeInit()
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self.serdes = FakeSerdes()
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class DUTScrambler(Module):
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def __init__(self):
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self.submodules.scrambler = scrambler.Scrambler(sync_interval=16)
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self.submodules.descrambler = scrambler.Descrambler()
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self.comb += [
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self.scrambler.source.connect(self.descrambler.sink),
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self.descrambler.source.ready.eq(1)
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]
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class DUTCore(Module):
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def __init__(self, **kwargs):
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# wishbone slave
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phy_slave = FakePHY()
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serwb_slave = SERWBCore(phy_slave, int(1e6), "slave", **kwargs)
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self.submodules += phy_slave, serwb_slave
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# wishbone master
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phy_master = FakePHY()
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serwb_master = SERWBCore(phy_master, int(1e6), "master", **kwargs)
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self.submodules += phy_master, serwb_master
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# connect phy
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self.comb += [
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phy_master.serdes.rx_k.eq(phy_slave.serdes.tx_k),
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phy_master.serdes.rx_d.eq(phy_slave.serdes.tx_d),
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phy_slave.serdes.rx_k.eq(phy_master.serdes.tx_k),
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phy_slave.serdes.rx_d.eq(phy_master.serdes.tx_d)
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]
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# add wishbone sram to wishbone master
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sram = SRAM(1024, bus=serwb_master.etherbone.wishbone.bus)
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self.submodules += sram
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# expose wishbone slave
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self.wishbone = serwb_slave.etherbone.wishbone.bus
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class TestSERWBCore(unittest.TestCase):
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def test_scrambler(self):
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def generator(dut):
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i = 0
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last_data = -1
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while i != 256:
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# stim
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if (yield dut.scrambler.sink.ready):
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i += 1
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yield dut.scrambler.sink.data.eq(i)
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# check
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if (yield dut.descrambler.source.valid):
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current_data = (yield dut.descrambler.source.data)
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if (current_data != (last_data + 1)):
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dut.errors += 1
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last_data = current_data
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# cycle
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yield
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dut = DUTScrambler()
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dut.errors = 0
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run_simulation(dut, generator(dut))
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self.assertEqual(dut.errors, 0)
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def test_serwb(self):
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def generator(dut):
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# prepare test
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prng = random.Random(42)
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data_base = 0x100
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data_length = 4
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datas_w = [prng.randrange(2**32) for i in range(data_length)]
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datas_r = []
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# write
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for i in range(data_length):
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yield from dut.wishbone.write(data_base + i, datas_w[i])
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# read
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for i in range(data_length):
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datas_r.append((yield from dut.wishbone.read(data_base + i)))
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# check
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for i in range(data_length):
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if datas_r[i] != datas_w[i]:
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dut.errors += 1
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# scrambling off
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dut = DUTCore(with_scrambling=False)
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dut.errors = 0
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run_simulation(dut, generator(dut))
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self.assertEqual(dut.errors, 0)
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# scrambling on
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dut = DUTCore(with_scrambling=True)
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dut.errors = 0
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run_simulation(dut, generator(dut))
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self.assertEqual(dut.errors, 0)
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@ -4,6 +4,7 @@ import unittest
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from migen import *
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from artiq.gateware.serwb import packet
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from artiq.gateware.serwb import etherbone
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from artiq.gateware.serwb.phy import _SerdesMasterInit, _SerdesSlaveInit
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@ -115,7 +116,7 @@ def generator(test, dut, valid_bitslip, valid_delays, check_success):
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test.assertEqual(error, 1)
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class TestSERWBInit(unittest.TestCase):
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class TestPHYInit(unittest.TestCase):
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def test_master_init_success(self):
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dut = DUTMaster()
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valid_bitslip = 2
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