forked from M-Labs/artiq
sayma: fix AD9154NoSAWG ramp clock domain
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@ -107,7 +107,7 @@ class AD9154NoSAWG(Module, AutoCSR):
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for i, conv in enumerate(self.jesd.core.sink.flatten()):
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ramp = Signal(16)
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self.sync += ramp.eq(ramp + (1 << 9 + i))
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self.sync.rtio += ramp.eq(ramp + (1 << 9 + i))
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self.comb += conv.eq(Cat(ramp
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for i in range(len(conv) // len(ramp))))
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