forked from M-Labs/artiq
targets: avoid passing cpu_type around unnecessarily
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parent
6d58c4390b
commit
7c82fcf41a
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@ -80,9 +80,9 @@ class _KasliBase(MiniSoC, AMPSoC):
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, cpu_type="or1k", **kwargs):
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type=cpu_type,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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@ -147,8 +147,8 @@ class Opticlock(_KasliBase):
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"""
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Opticlock extension configuration
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_KasliBase.__init__(self, cpu_type, **kwargs)
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def __init__(self, **kwargs):
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_KasliBase.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(_dio("eem0"))
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@ -210,9 +210,9 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, cpu_type="or1k", **kwargs):
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type=cpu_type,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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@ -277,8 +277,8 @@ class NIST_CLOCK(_NIST_Ions):
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"""
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NIST clock hardware, with old backplane and 11 DDS channels
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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def __init__(self, **kwargs):
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_NIST_Ions.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_clock.fmc_adapter_io)
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@ -379,8 +379,8 @@ class NIST_QC2(_NIST_Ions):
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 24 DDS channels. Two backplanes are used.
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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def __init__(self, **kwargs):
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_NIST_Ions.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_qc2.fmc_adapter_io)
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@ -81,8 +81,8 @@ class SMA_SPI(_NIST_Ions):
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"""
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SPI on 4 SMA for PDQ2 test/demo.
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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def __init__(self, **kwargs):
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_NIST_Ions.__init__(self, **kwargs)
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platform = self.platform
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self.platform.add_extension(_sma_spi)
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@ -122,9 +122,9 @@ class Standalone(MiniSoC, AMPSoC):
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, cpu_type="or1k", with_sawg=False, **kwargs):
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def __init__(self, with_sawg=False, **kwargs):
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MiniSoC.__init__(self,
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cpu_type=cpu_type,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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