forked from M-Labs/artiq
sayma,kasli: use new pin names
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parent
8598e475e9
commit
5198c224a2
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@ -14,7 +14,7 @@ from artiq.gateware.drtio.transceiver.gth_ultrascale_init import *
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class GTHSingle(Module):
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def __init__(self, refclk, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, dw, mode):
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def __init__(self, refclk, pads, sys_clk_freq, rtio_clk_freq, dw, mode):
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assert (dw == 20) or (dw == 40)
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assert mode in ["master", "slave"]
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@ -167,10 +167,10 @@ class GTHSingle(Module):
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i_RXELECIDLEMODE=0b11,
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# Pads
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i_GTHRXP=rx_pads.p,
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i_GTHRXN=rx_pads.n,
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o_GTHTXP=tx_pads.p,
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o_GTHTXN=tx_pads.n
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i_GTHRXP=pads.rxp,
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i_GTHRXN=pads.rxn,
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o_GTHTXP=pads.txp,
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o_GTHTXN=pads.txn
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)
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self.submodules += [
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@ -222,8 +222,8 @@ class GTHSingle(Module):
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class GTH(Module, TransceiverInterface):
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, dw=20, master=0):
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self.nchannels = nchannels = len(tx_pads)
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def __init__(self, clock_pads, data_pads, sys_clk_freq, rtio_clk_freq, dw=20, master=0):
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self.nchannels = nchannels = len(data_pads)
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self.gths = []
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# # #
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@ -239,7 +239,7 @@ class GTH(Module, TransceiverInterface):
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channel_interfaces = []
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for i in range(nchannels):
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mode = "master" if i == master else "slave"
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gth = GTHSingle(refclk, tx_pads[i], rx_pads[i], sys_clk_freq, rtio_clk_freq, dw, mode)
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gth = GTHSingle(refclk, data_pads[i], sys_clk_freq, rtio_clk_freq, dw, mode)
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if mode == "master":
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self.comb += rtio_tx_clk.eq(gth.cd_rtio_tx.clk)
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else:
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@ -12,7 +12,7 @@ from artiq.gateware.drtio.transceiver.gtp_7series_init import *
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class GTPSingle(Module):
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def __init__(self, qpll_channel, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, mode):
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def __init__(self, qpll_channel, pads, sys_clk_freq, rtio_clk_freq, mode):
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if mode != "master":
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raise NotImplementedError
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self.submodules.encoder = encoder = ClockDomainsRenamer("rtio_tx")(
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@ -163,10 +163,10 @@ class GTPSingle(Module):
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o_RXDATA=Cat(rxdata[:8], rxdata[10:18]),
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# Pads
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i_GTPRXP=rx_pads.p,
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i_GTPRXN=rx_pads.n,
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o_GTPTXP=tx_pads.p,
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o_GTPTXN=tx_pads.n
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i_GTPRXP=pads.rxp,
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i_GTPRXN=pads.rxn,
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o_GTPTXP=pads.txp,
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o_GTPTXN=pads.txn
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)
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# tx clocking
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@ -215,8 +215,8 @@ class GTPSingle(Module):
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class GTP(Module, TransceiverInterface):
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def __init__(self, qpll_channel, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, master=0):
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self.nchannels = nchannels = len(tx_pads)
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def __init__(self, qpll_channel, data_pads, sys_clk_freq, rtio_clk_freq, master=0):
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self.nchannels = nchannels = len(data_pads)
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self.gtps = []
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if nchannels >= 1:
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raise NotImplementedError
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@ -227,7 +227,7 @@ class GTP(Module, TransceiverInterface):
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channel_interfaces = []
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for i in range(nchannels):
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mode = "master" if i == master else "slave"
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gtp = GTPSingle(qpll_channel, tx_pads[i], rx_pads[i], sys_clk_freq, rtio_clk_freq, mode)
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gtp = GTPSingle(qpll_channel, data_pads[i], sys_clk_freq, rtio_clk_freq, mode)
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if mode == "master":
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self.comb += rtio_tx_clk.eq(gtp.cd_rtio_tx.clk)
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else:
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@ -30,14 +30,14 @@ class _RTIOCRG(Module, AutoCSR):
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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rtio_external_clk = Signal()
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clk_fpgaio_se = Signal()
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clk_fpgaio = platform.request("clk_fpgaio") # from Si5324
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platform.add_period_constraint(clk_fpgaio.p, 8.0)
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clk_synth_se = Signal()
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clk_synth = platform.request("si5324_clkout_fabric")
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
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i_I=clk_fpgaio.p, i_IB=clk_fpgaio.n, o_O=clk_fpgaio_se),
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Instance("BUFG", i_I=clk_fpgaio_se, o_O=rtio_external_clk),
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
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Instance("BUFG", i_I=clk_synth_se, o_O=rtio_external_clk),
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]
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pll_locked = Signal()
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@ -169,8 +169,8 @@ class Opticlock(_KasliBase):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in (1, 2):
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sfp = platform.request("sfp", i)
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phy = ttl_simple.Output(sfp.led)
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sfp_ctl = platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -61,8 +61,7 @@ class Master(MiniSoC, AMPSoC):
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self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
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self.submodules.transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=[platform.request("sfp_tx", 0)],
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rx_pads=[platform.request("sfp_rx", 0)],
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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@ -63,8 +63,7 @@ class Satellite(BaseSoC):
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self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
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self.submodules.transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=[platform.request("sfp_tx", 0)],
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rx_pads=[platform.request("sfp_rx", 0)],
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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