forked from M-Labs/artiq
kc705_dds: make ext_clkout 100 MHz
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43686f324b
commit
c2be820e9a
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@ -29,12 +29,11 @@ class _RTIOCRG(Module, AutoCSR):
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# 10 MHz when using 125MHz input
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# 100 MHz when using 125MHz input
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self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
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ext_clkout = platform.request("user_sma_gpio_p_33")
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self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
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rtio_external_clk = Signal()
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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@ -66,7 +65,7 @@ class _RTIOCRG(Module, AutoCSR):
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=50, p_CLKOUT1_PHASE=0.0,
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p_CLKOUT1_DIVIDE=5, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=ext_clkout_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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