forked from M-Labs/artiq
sayma: rtio clock is jesd fabric clock
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3eb882b6b7
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7405006668
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@ -220,8 +220,8 @@ class Standalone(MiniSoC, AMPSoC):
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self.clock_domains.cd_rtio = ClockDomain()
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self.comb += [
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self.cd_rtio.clk.eq(ClockSignal()),
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self.cd_rtio.rst.eq(ResetSignal())
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self.cd_rtio.clk.eq(ClockSignal("jesd")),
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self.cd_rtio.rst.eq(ResetSignal("jesd"))
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]
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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