forked from M-Labs/artiq
gateware/serwb: cleanup packet
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08dada9e16
commit
7f4756a869
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@ -89,34 +89,31 @@ class Packetizer(Module):
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# - length : 4 bytes
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# - payload
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fsm = FSM(reset_state="IDLE")
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fsm = FSM(reset_state="PREAMBLE")
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self.submodules += fsm
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fsm.act("IDLE",
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fsm.act("PREAMBLE",
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If(sink.stb,
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NextState("INSERT_PREAMBLE")
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source.stb.eq(1),
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source.data.eq(0x5aa55aa5),
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If(source.ack,
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NextState("LENGTH")
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)
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)
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)
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fsm.act("INSERT_PREAMBLE",
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source.stb.eq(1),
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source.data.eq(0x5aa55aa5),
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If(source.ack,
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NextState("INSERT_LENGTH")
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)
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)
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fsm.act("INSERT_LENGTH",
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fsm.act("LENGTH",
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source.stb.eq(1),
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source.data.eq(sink.length),
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If(source.ack,
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NextState("COPY")
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NextState("DATA")
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)
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)
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fsm.act("COPY",
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fsm.act("DATA",
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source.stb.eq(sink.stb),
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source.data.eq(sink.data),
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sink.ack.eq(source.ack),
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If(source.ack & sink.eop,
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NextState("IDLE")
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NextState("PREAMBLE")
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)
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)
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@ -128,45 +125,49 @@ class Depacketizer(Module):
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# # #
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count = Signal(len(source.length))
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length = Signal(len(source.length))
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# Packet description
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# - preamble : 4 bytes
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# - length : 4 bytes
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# - payload
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fsm = FSM(reset_state="IDLE")
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fsm = FSM(reset_state="PREAMBLE")
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self.submodules += fsm
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self.submodules.timer = WaitTimer(clk_freq*timeout)
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self.comb += self.timer.wait.eq(~fsm.ongoing("IDLE"))
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timer = WaitTimer(clk_freq*timeout)
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self.submodules += timer
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fsm.act("IDLE",
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fsm.act("PREAMBLE",
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sink.ack.eq(1),
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If(sink.stb & (sink.data == 0x5aa55aa5),
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NextState("RECEIVE_LENGTH")
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If(sink.stb &
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(sink.data == 0x5aa55aa5),
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NextState("LENGTH")
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)
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)
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fsm.act("RECEIVE_LENGTH",
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fsm.act("LENGTH",
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sink.ack.eq(1),
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If(sink.stb,
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NextValue(source.length, sink.data),
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NextState("COPY")
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)
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NextValue(count, 0),
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NextValue(length, sink.data),
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NextState("DATA")
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),
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timer.wait.eq(1)
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)
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eop = Signal()
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cnt = Signal(32)
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fsm.act("COPY",
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fsm.act("DATA",
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source.stb.eq(sink.stb),
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source.eop.eq(eop),
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source.eop.eq(count == (length[2:] - 1)),
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source.length.eq(length),
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source.data.eq(sink.data),
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sink.ack.eq(source.ack),
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If((source.stb & source.ack & eop) | self.timer.done,
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NextState("IDLE")
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)
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)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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cnt.eq(0)
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If(timer.done,
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NextState("PREAMBLE")
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).Elif(source.stb & source.ack,
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cnt.eq(cnt + 1)
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)
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self.comb += eop.eq(cnt == source.length[2:] - 1)
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NextValue(count, count + 1),
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If(source.eop,
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NextState("PREAMBLE")
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)
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),
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timer.wait.eq(1)
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)
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