forked from M-Labs/artiq
sayma_rtm: constrain serwb clock input
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@ -148,6 +148,7 @@ class SaymaRTM(Module):
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self.submodules += serwb_pll
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serwb_pads = platform.request("amc_rtm_serwb")
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platform.add_period_constraint(serwb_pads.clk_p, 16.)
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serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="slave")
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self.submodules.serwb_phy_rtm = serwb_phy_rtm
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self.comb += self.crg.reset.eq(serwb_phy_rtm.init.reset)
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