pounder_test/src/main.rs

998 lines
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Rust
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#![deny(warnings)]
#![allow(clippy::missing_safety_doc)]
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#![no_std]
#![no_main]
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#![cfg_attr(feature = "nightly", feature(asm))]
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// Enable returning `!`
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#![cfg_attr(feature = "nightly", feature(never_type))]
#![cfg_attr(feature = "nightly", feature(core_intrinsics))]
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#[inline(never)]
#[panic_handler]
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#[cfg(all(feature = "nightly", not(feature = "semihosting")))]
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fn panic(_info: &core::panic::PanicInfo) -> ! {
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let gpiod = unsafe { &*hal::stm32::GPIOD::ptr() };
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gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3
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#[cfg(feature = "nightly")]
core::intrinsics::abort();
#[cfg(not(feature = "nightly"))]
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unsafe {
core::intrinsics::abort();
}
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}
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#[cfg(feature = "semihosting")]
extern crate panic_semihosting;
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#[cfg(not(any(feature = "nightly", feature = "semihosting")))]
extern crate panic_halt;
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#[macro_use]
extern crate log;
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// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
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use cortex_m_rt::exception;
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use rtic::cyccnt::{Instant, U32Ext};
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use stm32h7xx_hal as hal;
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use stm32h7xx_hal::prelude::*;
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use embedded_hal::digital::v2::{InputPin, OutputPin};
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use hal::{
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dma::{
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config::Priority,
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dma::{DMAReq, DmaConfig},
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traits::TargetAddress,
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MemoryToPeripheral, PeripheralToMemory, Transfer,
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},
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ethernet::{self, PHY},
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};
use smoltcp as net;
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use smoltcp::iface::Routes;
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use smoltcp::wire::Ipv4Address;
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use heapless::{consts::*, String};
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// The desired sampling frequency of the ADCs.
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const SAMPLE_FREQUENCY_KHZ: u32 = 500;
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// The desired ADC sample processing buffer size.
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const SAMPLE_BUFFER_SIZE: usize = 2;
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#[link_section = ".sram3.eth"]
static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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mod adc;
mod afe;
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mod dac;
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mod design_parameters;
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mod eeprom;
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mod hrtimer;
mod pounder;
mod sampling_timer;
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mod server;
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use adc::{Adc0Input, Adc1Input};
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use dac::{Dac0Output, Dac1Output};
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use dsp::iir;
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use pounder::DdsOutput;
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#[cfg(not(feature = "semihosting"))]
fn init_log() {}
#[cfg(feature = "semihosting")]
fn init_log() {
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use cortex_m_log::log::{init as init_log, Logger};
use cortex_m_log::printer::semihosting::{hio::HStdout, InterruptOk};
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use log::LevelFilter;
static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
let logger = Logger {
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inner: InterruptOk::<_>::stdout().unwrap(),
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level: LevelFilter::Info,
};
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let logger = unsafe { LOGGER.get_or_insert(logger) };
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init_log(logger).unwrap();
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}
// Pull in build information (from `built` crate)
mod build_info {
#![allow(dead_code)]
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// include!(concat!(env!("OUT_DIR"), "/built.rs"));
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}
pub struct NetStorage {
ip_addrs: [net::wire::IpCidr; 1],
neighbor_cache: [Option<(net::wire::IpAddress, net::iface::Neighbor)>; 8],
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routes_storage: [Option<(smoltcp::wire::IpCidr, smoltcp::iface::Route)>; 1],
}
static mut NET_STORE: NetStorage = NetStorage {
// Placeholder for the real IP address, which is initialized at runtime.
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ip_addrs: [net::wire::IpCidr::Ipv6(
net::wire::Ipv6Cidr::SOLICITED_NODE_PREFIX,
)],
neighbor_cache: [None; 8],
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routes_storage: [None; 1],
};
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
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const TCP_RX_BUFFER_SIZE: usize = 8192;
const TCP_TX_BUFFER_SIZE: usize = 8192;
type AFE0 = afe::ProgrammableGainAmplifier<
hal::gpio::gpiof::PF2<hal::gpio::Output<hal::gpio::PushPull>>,
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hal::gpio::gpiof::PF5<hal::gpio::Output<hal::gpio::PushPull>>,
>;
type AFE1 = afe::ProgrammableGainAmplifier<
hal::gpio::gpiod::PD14<hal::gpio::Output<hal::gpio::PushPull>>,
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hal::gpio::gpiod::PD15<hal::gpio::Output<hal::gpio::PushPull>>,
>;
macro_rules! route_request {
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($request:ident,
readable_attributes: [$($read_attribute:tt: $getter:tt),*],
modifiable_attributes: [$($write_attribute:tt: $TYPE:ty, $setter:tt),*]) => {
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match $request.req {
server::AccessRequest::Read => {
match $request.attribute {
$(
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$read_attribute => {
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#[allow(clippy::redundant_closure_call)]
let value = match $getter() {
Ok(data) => data,
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Err(_) => return server::Response::error($request.attribute,
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"Failed to read attribute"),
};
let encoded_data: String<U256> = match serde_json_core::to_string(&value) {
Ok(data) => data,
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Err(_) => return server::Response::error($request.attribute,
"Failed to encode attribute value"),
};
server::Response::success($request.attribute, &encoded_data)
},
)*
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_ => server::Response::error($request.attribute, "Unknown attribute")
}
},
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server::AccessRequest::Write => {
match $request.attribute {
$(
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$write_attribute => {
let new_value = match serde_json_core::from_str::<$TYPE>(&$request.value) {
Ok(data) => data,
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Err(_) => return server::Response::error($request.attribute,
"Failed to decode value"),
};
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#[allow(clippy::redundant_closure_call)]
match $setter(new_value) {
Ok(_) => server::Response::success($request.attribute, &$request.value),
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Err(_) => server::Response::error($request.attribute,
"Failed to set attribute"),
}
}
)*
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_ => server::Response::error($request.attribute, "Unknown attribute")
}
}
}
}
}
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adcs: (Adc0Input, Adc1Input),
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dacs: (Dac0Output, Dac1Output),
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eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
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dds_output: Option<DdsOutput>,
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// Note: It appears that rustfmt generates a format that GDB cannot recognize, which
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// results in GDB breakpoints being set improperly.
#[rustfmt::skip]
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net_interface: net::iface::EthernetInterface<
'static,
'static,
'static,
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ethernet::EthernetDMA<'static>>,
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eth_mac: ethernet::phy::LAN8742A<ethernet::EthernetMAC>,
mac_addr: net::wire::EthernetAddress,
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pounder: Option<pounder::PounderDevices>,
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#[init([[0.; 5]; 2])]
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iir_state: [iir::IIRState; 2],
#[init([iir::IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; 2])]
iir_ch: [iir::IIR; 2],
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}
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#[init]
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fn init(c: init::Context) -> init::LateResources {
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let dp = c.device;
let mut cp = c.core;
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let pwr = dp.PWR.constrain();
let vos = pwr.freeze();
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// Enable SRAM3 for the ethernet descriptor ring.
dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
// Clear reset flags.
dp.RCC.rsr.write(|w| w.rmvf().set_bit());
// Select the PLLs for SPI.
dp.RCC
.d2ccip1r
.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
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let rcc = dp.RCC.constrain();
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let ccdr = rcc
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.use_hse(8.mhz())
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.sysclk(400.mhz())
.hclk(200.mhz())
.per_ck(100.mhz())
.pll2_p_ck(100.mhz())
.pll2_q_ck(100.mhz())
.freeze(vos, &dp.SYSCFG);
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init_log();
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let mut delay = hal::delay::Delay::new(cp.SYST, ccdr.clocks);
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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let mut gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
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let afe0 = {
let a0_pin = gpiof.pf2.into_push_pull_output();
let a1_pin = gpiof.pf5.into_push_pull_output();
afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
};
let afe1 = {
let a0_pin = gpiod.pd14.into_push_pull_output();
let a1_pin = gpiod.pd15.into_push_pull_output();
afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
};
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let dma_streams =
hal::dma::dma::StreamsTuple::new(dp.DMA1, ccdr.peripheral.DMA1);
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// Configure timer 2 to trigger conversions for the ADC
let timer2 = dp.TIM2.timer(
SAMPLE_FREQUENCY_KHZ.khz(),
ccdr.peripheral.TIM2,
&ccdr.clocks,
);
let mut sampling_timer = sampling_timer::SamplingTimer::new(timer2);
let sampling_timer_channels = sampling_timer.channels();
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// Configure the SPI interfaces to the ADCs and DACs.
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let adcs = {
let adc0 = {
let spi_miso = gpiob
.pb14
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpiob
.pb10
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let _spi_nss = gpiob
.pb9
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
})
.manage_cs()
.suspend_when_inactive()
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.cs_delay(design_parameters::ADC_SETUP_TIME);
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let spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi(
(spi_sck, spi_miso, hal::spi::NoMosi),
config,
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design_parameters::ADC_DAC_SCK_MHZ_MAX.mhz(),
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ccdr.peripheral.SPI2,
&ccdr.clocks,
);
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Adc0Input::new(
spi,
dma_streams.0,
dma_streams.1,
sampling_timer_channels.ch1,
)
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};
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let adc1 = {
let spi_miso = gpiob
.pb4
.into_alternate_af6()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpioc
.pc10
.into_alternate_af6()
.set_speed(hal::gpio::Speed::VeryHigh);
let _spi_nss = gpioa
.pa15
.into_alternate_af6()
.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
})
.manage_cs()
.suspend_when_inactive()
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.cs_delay(design_parameters::ADC_SETUP_TIME);
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let spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi(
(spi_sck, spi_miso, hal::spi::NoMosi),
config,
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design_parameters::ADC_DAC_SCK_MHZ_MAX.mhz(),
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ccdr.peripheral.SPI3,
&ccdr.clocks,
);
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Adc1Input::new(
spi,
dma_streams.2,
dma_streams.3,
sampling_timer_channels.ch2,
)
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};
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(adc0, adc1)
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};
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let dacs = {
let _dac_clr_n =
gpioe.pe12.into_push_pull_output().set_high().unwrap();
let _dac0_ldac_n =
gpioe.pe11.into_push_pull_output().set_low().unwrap();
let _dac1_ldac_n =
gpioe.pe15.into_push_pull_output().set_low().unwrap();
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let dac0_spi = {
let spi_miso = gpioe
.pe5
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpioe
.pe2
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let _spi_nss = gpioe
.pe4
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
})
.manage_cs()
.suspend_when_inactive()
.communication_mode(hal::spi::CommunicationMode::Transmitter)
.swap_mosi_miso();
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dp.SPI4.spi(
(spi_sck, spi_miso, hal::spi::NoMosi),
config,
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design_parameters::ADC_DAC_SCK_MHZ_MAX.mhz(),
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ccdr.peripheral.SPI4,
&ccdr.clocks,
)
};
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let dac1_spi = {
let spi_miso = gpiof
.pf8
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpiof
.pf7
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let _spi_nss = gpiof
.pf6
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
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let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
})
.manage_cs()
.communication_mode(hal::spi::CommunicationMode::Transmitter)
.suspend_when_inactive()
.swap_mosi_miso();
dp.SPI5.spi(
(spi_sck, spi_miso, hal::spi::NoMosi),
config,
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design_parameters::ADC_DAC_SCK_MHZ_MAX.mhz(),
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ccdr.peripheral.SPI5,
&ccdr.clocks,
)
};
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let dac0 = Dac0Output::new(
dac0_spi,
dma_streams.4,
sampling_timer_channels.ch3,
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);
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let dac1 = Dac1Output::new(
dac1_spi,
dma_streams.5,
sampling_timer_channels.ch4,
);
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(dac0, dac1)
};
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let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
let mut fp_led_1 = gpiod.pd6.into_push_pull_output();
let mut fp_led_2 = gpiog.pg4.into_push_pull_output();
let mut fp_led_3 = gpiod.pd12.into_push_pull_output();
fp_led_0.set_low().unwrap();
fp_led_1.set_low().unwrap();
fp_led_2.set_low().unwrap();
fp_led_3.set_low().unwrap();
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// Measure the Pounder PGOOD output to detect if pounder is present on Stabilizer.
let pounder_pgood = gpiob.pb13.into_pull_down_input();
delay.delay_ms(2u8);
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let (pounder_devices, dds_output) = if pounder_pgood.is_high().unwrap()
{
let mut ad9959 = {
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let qspi_interface = {
// Instantiate the QUADSPI pins and peripheral interface.
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let qspi_pins = {
let _qspi_ncs = gpioc
.pc11
.into_alternate_af9()
.set_speed(hal::gpio::Speed::VeryHigh);
let clk = gpiob
.pb2
.into_alternate_af9()
.set_speed(hal::gpio::Speed::VeryHigh);
let io0 = gpioe
.pe7
.into_alternate_af10()
.set_speed(hal::gpio::Speed::VeryHigh);
let io1 = gpioe
.pe8
.into_alternate_af10()
.set_speed(hal::gpio::Speed::VeryHigh);
let io2 = gpioe
.pe9
.into_alternate_af10()
.set_speed(hal::gpio::Speed::VeryHigh);
let io3 = gpioe
.pe10
.into_alternate_af10()
.set_speed(hal::gpio::Speed::VeryHigh);
(clk, io0, io1, io2, io3)
};
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let qspi = hal::qspi::Qspi::bank2(
dp.QUADSPI,
qspi_pins,
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40.mhz(),
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&ccdr.clocks,
ccdr.peripheral.QSPI,
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);
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pounder::QspiInterface::new(qspi).unwrap()
};
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let reset_pin = gpioa.pa0.into_push_pull_output();
let mut io_update = gpiog.pg7.into_push_pull_output();
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let ad9959 = ad9959::Ad9959::new(
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qspi_interface,
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reset_pin,
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&mut io_update,
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&mut delay,
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ad9959::Mode::FourBitSerial,
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100_000_000_f32,
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5,
)
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.unwrap();
// Return IO_Update
gpiog.pg7 = io_update.into_analog();
ad9959
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};
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let io_expander = {
let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
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let i2c1 = dp.I2C1.i2c(
(scl, sda),
100.khz(),
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ccdr.peripheral.I2C1,
&ccdr.clocks,
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);
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mcp23017::MCP23017::default(i2c1).unwrap()
};
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let spi = {
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let spi_mosi = gpiod
.pd7
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_miso = gpioa
.pa6
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpiog
.pg11
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
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});
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// The maximum frequency of this SPI must be limited due to capacitance on the MISO
// line causing a long RC decay.
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dp.SPI1.spi(
(spi_sck, spi_miso, spi_mosi),
config,
5.mhz(),
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ccdr.peripheral.SPI1,
&ccdr.clocks,
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)
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};
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let (adc1, adc2) = {
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let (mut adc1, mut adc2) = hal::adc::adc12(
dp.ADC1,
dp.ADC2,
&mut delay,
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ccdr.peripheral.ADC12,
&ccdr.clocks,
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);
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let adc1 = {
adc1.calibrate();
adc1.enable()
};
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let adc2 = {
adc2.calibrate();
adc2.enable()
};
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(adc1, adc2)
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};
let adc1_in_p = gpiof.pf11.into_analog();
let adc2_in_p = gpiof.pf14.into_analog();
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let pounder_devices = pounder::PounderDevices::new(
io_expander,
&mut ad9959,
spi,
adc1,
adc2,
adc1_in_p,
adc2_in_p,
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)
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.unwrap();
let dds_output = {
let io_update_trigger = {
let _io_update = gpiog
.pg7
.into_alternate_af2()
.set_speed(hal::gpio::Speed::VeryHigh);
// Configure the IO_Update signal for the DDS.
let mut hrtimer = hrtimer::HighResTimerE::new(
dp.HRTIM_TIME,
dp.HRTIM_MASTER,
dp.HRTIM_COMMON,
ccdr.clocks,
ccdr.peripheral.HRTIM,
);
// IO_Update should be latched for 50ns after the QSPI profile write. Profile writes
// are always 16 bytes, with 2 cycles required per byte, coming out to a total of 32
// QSPI clock cycles. The QSPI is configured for 40MHz, so this comes out to an
// offset of 800nS. We use 900ns to be safe - note that the timer is triggered after
// the QSPI write, which can take approximately 120nS, so there is additional
// margin.
hrtimer.configure_single_shot(
hrtimer::Channel::Two,
50_e-9,
900_e-9,
);
// Ensure that we have enough time for an IO-update every sample.
assert!(
1.0 / (1000 * SAMPLE_FREQUENCY_KHZ) as f32 > 900_e-9
);
hrtimer
};
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let (mut qspi, config) = ad9959.freeze();
qspi.start_stream().unwrap();
DdsOutput::new(qspi, io_update_trigger, config)
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};
(Some(pounder_devices), Some(dds_output))
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} else {
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(None, None)
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};
let mut eeprom_i2c = {
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let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
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dp.I2C2.i2c(
(scl, sda),
100.khz(),
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ccdr.peripheral.I2C2,
&ccdr.clocks,
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)
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};
// Configure ethernet pins.
{
// Reset the PHY before configuring pins.
let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
eth_phy_nrst.set_low().unwrap();
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delay.delay_us(200u8);
eth_phy_nrst.set_high().unwrap();
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let _rmii_ref_clk = gpioa
.pa1
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_mdio = gpioa
.pa2
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_mdc = gpioc
.pc1
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_crs_dv = gpioa
.pa7
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_rxd0 = gpioc
.pc4
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_rxd1 = gpioc
.pc5
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_tx_en = gpiob
.pb11
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_txd0 = gpiob
.pb12
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_txd1 = gpiog
.pg14
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
}
let mac_addr = match eeprom::read_eui48(&mut eeprom_i2c) {
Err(_) => {
info!("Could not read EEPROM, using default MAC address");
net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00])
}
Ok(raw_mac) => net::wire::EthernetAddress(raw_mac),
};
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let (network_interface, eth_mac) = {
// Configure the ethernet controller
let (eth_dma, eth_mac) = unsafe {
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ethernet::new_unchecked(
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dp.ETHERNET_MAC,
dp.ETHERNET_MTL,
dp.ETHERNET_DMA,
&mut DES_RING,
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mac_addr,
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ccdr.peripheral.ETH1MAC,
&ccdr.clocks,
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)
};
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// Reset and initialize the ethernet phy.
let mut lan8742a =
ethernet::phy::LAN8742A::new(eth_mac.set_phy_addr(0));
lan8742a.phy_reset();
lan8742a.phy_init();
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unsafe { ethernet::enable_interrupt() };
let store = unsafe { &mut NET_STORE };
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store.ip_addrs[0] = net::wire::IpCidr::new(
net::wire::IpAddress::v4(10, 0, 16, 99),
24,
);
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let default_v4_gw = Ipv4Address::new(10, 0, 16, 1);
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let mut routes = Routes::new(&mut store.routes_storage[..]);
routes.add_default_ipv4_route(default_v4_gw).unwrap();
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let neighbor_cache =
net::iface::NeighborCache::new(&mut store.neighbor_cache[..]);
let interface = net::iface::EthernetInterfaceBuilder::new(eth_dma)
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.ethernet_addr(mac_addr)
.neighbor_cache(neighbor_cache)
.ip_addrs(&mut store.ip_addrs[..])
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.routes(routes)
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.finalize();
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(interface, lan8742a)
};
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cp.SCB.enable_icache();
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//cp.SCB.enable_dcache(&mut cp.CPUID);
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2019-05-31 00:03:48 +08:00
// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
// info!("Built on {}", build_info::BUILT_TIME_UTC);
// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
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// Utilize the cycle counter for RTIC scheduling.
cp.DWT.enable_cycle_counter();
// Start sampling ADCs.
sampling_timer.start();
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2019-05-31 04:57:41 +08:00
init::LateResources {
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afes: (afe0, afe1),
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adcs,
dacs,
dds_output,
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pounder: pounder_devices,
eeprom_i2c,
net_interface: network_interface,
eth_mac,
mac_addr,
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}
}
#[task(binds=DMA1_STR3, resources=[adcs, dacs, iir_state, iir_ch, dds_output], priority=2)]
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fn process(c: process::Context) {
let adc_samples = [
c.resources.adcs.0.acquire_buffer(),
c.resources.adcs.1.acquire_buffer(),
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];
let dac_samples = [
c.resources.dacs.0.acquire_buffer(),
c.resources.dacs.1.acquire_buffer(),
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];
for channel in 0..adc_samples.len() {
for sample in 0..adc_samples[0].len() {
let x = f32::from(adc_samples[channel][sample] as i16);
let y = c.resources.iir_ch[channel]
.update(&mut c.resources.iir_state[channel], x);
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// Note(unsafe): The filter limits ensure that the value is in range.
// The truncation introduces 1/2 LSB distortion.
let y = unsafe { y.to_int_unchecked::<i16>() };
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// Convert to DAC code
dac_samples[channel][sample] = y as u16 ^ 0x8000;
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}
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}
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if let Some(dds_output) = c.resources.dds_output {
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let builder = dds_output.builder().update_channels(
&[pounder::Channel::Out0.into()],
Some(u32::MAX / 4),
None,
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None,
);
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builder.write_profile();
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}
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let [dac0, dac1] = dac_samples;
c.resources.dacs.0.release_buffer(dac0);
c.resources.dacs.1.release_buffer(dac1);
}
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#[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afes])]
fn idle(mut c: idle::Context) -> ! {
let mut socket_set_entries: [_; 8] = Default::default();
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let mut sockets =
net::socket::SocketSet::new(&mut socket_set_entries[..]);
let mut rx_storage = [0; TCP_RX_BUFFER_SIZE];
let mut tx_storage = [0; TCP_TX_BUFFER_SIZE];
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let tcp_handle = {
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let tcp_rx_buffer =
net::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
let tcp_tx_buffer =
net::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
let tcp_socket =
net::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
sockets.add(tcp_socket)
};
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let mut server = server::Server::new();
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let mut time = 0u32;
let mut next_ms = Instant::now();
// TODO: Replace with reference to CPU clock from CCDR.
next_ms += 400_000.cycles();
loop {
let tick = Instant::now() > next_ms;
if tick {
next_ms += 400_000.cycles();
time += 1;
}
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{
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let socket =
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&mut *sockets.get::<net::socket::TcpSocket>(tcp_handle);
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if socket.state() == net::socket::TcpState::CloseWait {
socket.close();
} else if !(socket.is_open() || socket.is_listening()) {
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socket
.listen(1235)
.unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
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} else {
server.poll(socket, |req| {
info!("Got request: {:?}", req);
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route_request!(req,
readable_attributes: [
"stabilizer/iir/state": (|| {
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let state = c.resources.iir_state.lock(|iir_state|
server::Status {
t: time,
x0: iir_state[0][0],
y0: iir_state[0][2],
x1: iir_state[1][0],
y1: iir_state[1][2],
});
Ok::<server::Status, ()>(state)
}),
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"stabilizer/afe0/gain": (|| c.resources.afes.0.get_gain()),
"stabilizer/afe1/gain": (|| c.resources.afes.1.get_gain())
],
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modifiable_attributes: [
"stabilizer/iir0/state": server::IirRequest, (|req: server::IirRequest| {
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c.resources.iir_ch.lock(|iir_ch| {
if req.channel > 1 {
return Err(());
}
iir_ch[req.channel as usize] = req.iir;
Ok::<server::IirRequest, ()>(req)
})
}),
"stabilizer/iir1/state": server::IirRequest, (|req: server::IirRequest| {
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c.resources.iir_ch.lock(|iir_ch| {
if req.channel > 1 {
return Err(());
}
iir_ch[req.channel as usize] = req.iir;
Ok::<server::IirRequest, ()>(req)
})
}),
"stabilizer/afe0/gain": afe::Gain, (|gain| {
c.resources.afes.0.set_gain(gain);
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Ok::<(), ()>(())
}),
"stabilizer/afe1/gain": afe::Gain, (|gain| {
c.resources.afes.1.set_gain(gain);
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Ok::<(), ()>(())
})
]
)
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});
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}
}
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let sleep = match c.resources.net_interface.poll(
&mut sockets,
net::time::Instant::from_millis(time as i64),
) {
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Ok(changed) => !changed,
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Err(net::Error::Unrecognized) => true,
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Err(e) => {
info!("iface poll error: {:?}", e);
true
}
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};
if sleep {
cortex_m::asm::wfi();
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}
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}
}
2019-04-28 19:37:14 +08:00
2020-06-09 20:16:01 +08:00
#[task(binds = ETH, priority = 1)]
fn eth(_: eth::Context) {
unsafe { ethernet::interrupt_handler() }
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}
#[task(binds = SPI2, priority = 3)]
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fn spi2(_: spi2::Context) {
panic!("ADC0 input overrun");
}
#[task(binds = SPI3, priority = 3)]
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fn spi3(_: spi3::Context) {
panic!("ADC0 input overrun");
}
#[task(binds = SPI4, priority = 3)]
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fn spi4(_: spi4::Context) {
panic!("DAC0 output error");
}
#[task(binds = SPI5, priority = 3)]
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fn spi5(_: spi5::Context) {
panic!("DAC1 output error");
}
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extern "C" {
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// hw interrupt handlers for RTIC to use for scheduling tasks
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// one per priority
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fn DCMI();
fn JPEG();
fn SDMMC();
}
};
2019-03-18 19:56:26 +08:00
#[exception]
fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
panic!("HardFault at {:#?}", ef);
}
#[exception]
fn DefaultHandler(irqn: i16) {
panic!("Unhandled exception (IRQn = {})", irqn);
}