dacs: macros
This commit is contained in:
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1906185286
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427
src/dac.rs
427
src/dac.rs
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@ -11,306 +11,143 @@ use super::{
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// The following global buffers are used for the DAC code DMA transfers. Two buffers are used for
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// each transfer in a ping-pong buffer configuration (one is being prepared while the other is being
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// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on
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// startup are undefined.
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// startup are undefined. The dimension are `ADC_BUF[adc_index][ping_pong_index][sample_index]`.
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#[link_section = ".axisram.buffers"]
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static mut DAC0_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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static mut DAC_BUF: [[[u16; SAMPLE_BUFFER_SIZE]; 2]; 2] =
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[[[0; SAMPLE_BUFFER_SIZE]; 2]; 2];
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#[link_section = ".axisram.buffers"]
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static mut DAC0_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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#[link_section = ".axisram.buffers"]
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static mut DAC1_BUF0: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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#[link_section = ".axisram.buffers"]
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static mut DAC1_BUF1: [u16; SAMPLE_BUFFER_SIZE] = [0; SAMPLE_BUFFER_SIZE];
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/// SPI4 is used as a type for indicating a DMA transfer into the SPI4 TX FIFO
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struct SPI4 {
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spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Disabled, u16>,
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_channel: sampling_timer::tim2::Channel3,
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}
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impl SPI4 {
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pub fn new(
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_channel: sampling_timer::tim2::Channel3,
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spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Disabled, u16>,
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) -> Self {
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Self { _channel, spi }
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}
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}
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// Note(unsafe): This is safe because the DMA request line is logically owned by this module.
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// Additionally, the SPI is owned by this structure and is known to be configured for u16 word
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// sizes.
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unsafe impl TargetAddress<MemoryToPeripheral> for SPI4 {
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/// SPI2 is configured to operate using 16-bit transfer words.
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type MemSize = u16;
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/// SPI4 DMA requests are generated whenever TIM2 CH3 comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_CH3 as u8);
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/// Whenever the DMA request occurs, it should write into SPI4's TX FIFO.
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fn address(&self) -> u32 {
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&self.spi.inner().txdr as *const _ as u32
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}
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}
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/// SPI5 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI5 TX FIFO
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struct SPI5 {
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_channel: sampling_timer::tim2::Channel4,
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spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Disabled, u16>,
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}
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impl SPI5 {
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pub fn new(
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_channel: sampling_timer::tim2::Channel4,
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spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Disabled, u16>,
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) -> Self {
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Self { _channel, spi }
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}
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}
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// Note(unsafe): This is safe because the DMA request line is logically owned by this module.
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// Additionally, the SPI is owned by this structure and is known to be configured for u16 word
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// sizes.
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unsafe impl TargetAddress<MemoryToPeripheral> for SPI5 {
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/// SPI5 is configured to operate using 16-bit transfer words.
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type MemSize = u16;
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/// SPI5 DMA requests are generated whenever TIM2 CH4 comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_CH4 as u8);
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/// Whenever the DMA request occurs, it should write into SPI5's TX FIFO
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fn address(&self) -> u32 {
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&self.spi.inner().txdr as *const _ as u32
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}
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}
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/// Represents both DAC output channels.
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pub struct DacOutputs {
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dac0: Dac0Output,
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dac1: Dac1Output,
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}
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impl DacOutputs {
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/// Construct the DAC outputs.
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pub fn new(dac0: Dac0Output, dac1: Dac1Output) -> Self {
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Self { dac0, dac1 }
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}
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/// Borrow the next DAC output buffers to populate the DAC output codes in-place.
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///
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/// # Returns
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/// (dac0, dac1) where each value is a mutable reference to the output code array for DAC0 and
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/// DAC1 respectively.
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pub fn prepare_data(
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&mut self,
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) -> (
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&mut [u16; SAMPLE_BUFFER_SIZE],
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&mut [u16; SAMPLE_BUFFER_SIZE],
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) {
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(self.dac0.prepare_buffer(), self.dac1.prepare_buffer())
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}
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/// Enqueue the next DAC output codes for transmission.
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///
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/// # Note
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/// It is assumed that data was populated using `prepare_data()` before this function is
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/// called.
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pub fn commit_data(&mut self) {
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self.dac0.commit_buffer();
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self.dac1.commit_buffer();
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}
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}
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/// Represents data associated with DAC0.
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pub struct Dac0Output {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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// Note: SPI TX functionality may not be used from this structure to ensure safety with DMA.
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transfer: Transfer<
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hal::dma::dma::Stream4<hal::stm32::DMA1>,
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SPI4,
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MemoryToPeripheral,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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>,
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first_transfer: bool,
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}
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impl Dac0Output {
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/// Construct the DAC0 output channel.
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///
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/// # Args
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/// * `spi` - The SPI interface used to communicate with the ADC.
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/// * `stream` - The DMA stream used to write DAC codes over SPI.
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/// * `trigger_channel` - The sampling timer output compare channel for update triggers.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
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stream: hal::dma::dma::Stream4<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::tim2::Channel3,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(0);
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// The stream constantly writes to the TX FIFO to write new update codes.
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let trigger_config = DmaConfig::default()
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.memory_increment(true)
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.peripheral_increment(false);
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// Listen for any potential SPI error signals, which may indicate that we are not generating
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// update codes.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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// Construct the trigger stream to write from memory to the peripheral.
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let transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init(
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stream,
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SPI4::new(trigger_channel, spi),
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// Note(unsafe): This buffer is only used once and provided for the DMA transfer.
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unsafe { &mut DAC0_BUF0 },
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None,
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trigger_config,
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);
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Self {
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transfer,
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// Note(unsafe): This buffer is only used once and provided for the next DMA transfer.
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next_buffer: unsafe { Some(&mut DAC0_BUF1) },
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first_transfer: true,
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}
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}
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/// Mutably borrow the next output buffer to populate it with DAC codes.
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pub fn prepare_buffer(&mut self) -> &mut [u16; SAMPLE_BUFFER_SIZE] {
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self.next_buffer.as_mut().unwrap()
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}
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/// Enqueue the next buffer for transmission to the DAC.
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///
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/// # Args
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/// * `data` - The next data to write to the DAC.
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pub fn commit_buffer(&mut self) {
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let next_buffer = self.next_buffer.take().unwrap();
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// If the last transfer was not complete, we didn't write all our previous DAC codes.
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// Wait for all the DAC codes to get written as well.
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if self.first_transfer {
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self.first_transfer = false
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} else {
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// Note: If a device hangs up, check that this conditional is passing correctly, as
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// there is no time-out checks here in the interest of execution speed.
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while self.transfer.get_transfer_complete_flag() == false {}
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macro_rules! dac_output {
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($name:ident, $index:literal, $data_stream:ident,
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$spi:ident, $trigger_channel:ident, $dma_req:ident) => {
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/// SPI is used as a type for indicating a DMA transfer into the SPI TX FIFO
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struct $spi {
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Disabled, u16>,
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_channel: sampling_timer::tim2::$trigger_channel,
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}
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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self.next_buffer.replace(prev_buffer);
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}
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}
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/// Represents the data output stream from DAC1.
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pub struct Dac1Output {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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transfer: Transfer<
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hal::dma::dma::Stream5<hal::stm32::DMA1>,
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SPI5,
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MemoryToPeripheral,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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>,
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first_transfer: bool,
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}
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impl Dac1Output {
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/// Construct a new DAC1 output data stream.
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///
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/// # Args
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/// * `spi` - The SPI interface connected to DAC1.
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/// * `stream` - The DMA stream used to write DAC codes the SPI TX FIFO.
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/// * `trigger_channel` - The timer channel used to generate DMA requests for DAC updates.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
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stream: hal::dma::dma::Stream5<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::tim2::Channel4,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(0);
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// The trigger stream constantly writes to the TX FIFO to generate DAC updates.
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let trigger_config = DmaConfig::default()
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.memory_increment(true)
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.peripheral_increment(false)
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.circular_buffer(true);
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// Listen for any SPI errors, as this may indicate that we are not generating updates on the
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// DAC.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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// Construct the stream to write from memory to the peripheral.
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let transfer: Transfer<_, _, MemoryToPeripheral, _> = Transfer::init(
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stream,
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SPI5::new(trigger_channel, spi),
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// Note(unsafe): This buffer is only used once and provided to the transfer.
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unsafe { &mut DAC1_BUF0 },
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None,
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trigger_config,
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);
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Self {
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// Note(unsafe): This buffer is only used once and provided for the next DMA transfer.
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next_buffer: unsafe { Some(&mut DAC1_BUF1) },
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transfer,
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first_transfer: true,
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}
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}
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/// Mutably borrow the next output buffer to populate it with DAC codes.
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pub fn prepare_buffer(&mut self) -> &mut [u16; SAMPLE_BUFFER_SIZE] {
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self.next_buffer.as_mut().unwrap()
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}
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/// Enqueue the next buffer for transmission to the DAC.
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///
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/// # Args
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/// * `data` - The next data to write to the DAC.
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pub fn commit_buffer(&mut self) {
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let next_buffer = self.next_buffer.take().unwrap();
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// If the last transfer was not complete, we didn't write all our previous DAC codes.
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// Wait for all the DAC codes to get written as well.
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if self.first_transfer {
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self.first_transfer = false
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} else {
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// Note: If a device hangs up, check that this conditional is passing correctly, as
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// there is no time-out checks here in the interest of execution speed.
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while self.transfer.get_transfer_complete_flag() == false {}
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impl $spi {
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pub fn new(
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_channel: sampling_timer::tim2::$trigger_channel,
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Disabled, u16>,
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) -> Self {
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Self { _channel, spi }
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}
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}
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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// Note(unsafe): This is safe because the DMA request line is logically owned by this module.
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// Additionally, the SPI is owned by this structure and is known to be configured for u16 word
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// sizes.
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unsafe impl TargetAddress<MemoryToPeripheral> for $spi {
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/// SPI is configured to operate using 16-bit transfer words.
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type MemSize = u16;
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self.next_buffer.replace(prev_buffer);
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}
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/// SPI DMA requests are generated whenever TIM2 CH3 comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::$dma_req as u8);
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/// Whenever the DMA request occurs, it should write into SPI's TX FIFO.
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fn address(&self) -> u32 {
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&self.spi.inner().txdr as *const _ as u32
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}
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}
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/// Represents data associated with DAC0.
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pub struct $name {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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// Note: SPI TX functionality may not be used from this structure to ensure safety with DMA.
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transfer: Transfer<
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hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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$spi,
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MemoryToPeripheral,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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>,
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first_transfer: bool,
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}
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impl $name {
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/// Construct the DAC output channel.
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///
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/// # Args
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/// * `spi` - The SPI interface used to communicate with the ADC.
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/// * `stream` - The DMA stream used to write DAC codes over SPI.
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/// * `trigger_channel` - The sampling timer output compare channel for update triggers.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Enabled, u16>,
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stream: hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::tim2::$trigger_channel,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(0);
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// The stream constantly writes to the TX FIFO to write new update codes.
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let trigger_config = DmaConfig::default()
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.memory_increment(true)
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.peripheral_increment(false);
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// Listen for any potential SPI error signals, which may indicate that we are not generating
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// update codes.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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// Construct the trigger stream to write from memory to the peripheral.
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let transfer: Transfer<_, _, MemoryToPeripheral, _> =
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Transfer::init(
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stream,
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$spi::new(trigger_channel, spi),
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// Note(unsafe): This buffer is only used once and provided for the DMA transfer.
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unsafe { &mut DAC_BUF[$index][0] },
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None,
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trigger_config,
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);
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Self {
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transfer,
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// Note(unsafe): This buffer is only used once and provided for the next DMA transfer.
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next_buffer: unsafe { Some(&mut DAC_BUF[$index][1]) },
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first_transfer: true,
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}
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}
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/// Mutably borrow the next output buffer to populate it with DAC codes.
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pub fn prepare_buffer(&mut self) -> &mut [u16; SAMPLE_BUFFER_SIZE] {
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self.next_buffer.as_mut().unwrap()
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}
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/// Enqueue the next buffer for transmission to the DAC.
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///
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/// # Args
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/// * `data` - The next data to write to the DAC.
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pub fn commit_buffer(&mut self) {
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let next_buffer = self.next_buffer.take().unwrap();
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// If the last transfer was not complete, we didn't write all our previous DAC codes.
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// Wait for all the DAC codes to get written as well.
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if self.first_transfer {
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self.first_transfer = false
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} else {
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// Note: If a device hangs up, check that this conditional is passing correctly, as
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// there is no time-out checks here in the interest of execution speed.
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while self.transfer.get_transfer_complete_flag() == false {}
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}
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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self.next_buffer.replace(prev_buffer);
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}
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}
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};
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}
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dac_output!(Dac0Output, 0, Stream4, SPI4, Channel3, TIM2_CH3);
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dac_output!(Dac1Output, 1, Stream5, SPI5, Channel4, TIM2_CH4);
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12
src/main.rs
12
src/main.rs
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@ -70,7 +70,7 @@ mod sampling_timer;
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mod server;
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use adc::{Adc0Input, Adc1Input};
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use dac::{Dac0Output, Dac1Output, DacOutputs};
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use dac::{Dac0Output, Dac1Output};
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use dsp::iir;
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#[cfg(not(feature = "semihosting"))]
|
||||
|
|
@ -189,7 +189,7 @@ const APP: () = {
|
|||
afe1: AFE1,
|
||||
|
||||
adcs: (Adc0Input, Adc1Input),
|
||||
dacs: DacOutputs,
|
||||
dacs: (Dac0Output, Dac1Output),
|
||||
|
||||
eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
|
||||
|
||||
|
|
@ -441,7 +441,7 @@ const APP: () = {
|
|||
dma_streams.5,
|
||||
sampling_timer_channels.ch4,
|
||||
);
|
||||
DacOutputs::new(dac0, dac1)
|
||||
(dac0, dac1)
|
||||
};
|
||||
|
||||
let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
|
||||
|
|
@ -749,7 +749,8 @@ const APP: () = {
|
|||
let adc0_samples = c.resources.adcs.0.transfer_complete_handler();
|
||||
let adc1_samples = c.resources.adcs.1.transfer_complete_handler();
|
||||
|
||||
let (dac0, dac1) = c.resources.dacs.prepare_data();
|
||||
let dac0 = c.resources.dacs.0.prepare_buffer();
|
||||
let dac1 = c.resources.dacs.1.prepare_buffer();
|
||||
|
||||
for (i, (adc0, adc1)) in
|
||||
adc0_samples.iter().zip(adc1_samples.iter()).enumerate()
|
||||
|
|
@ -769,7 +770,8 @@ const APP: () = {
|
|||
};
|
||||
}
|
||||
|
||||
c.resources.dacs.commit_data();
|
||||
c.resources.dacs.0.commit_buffer();
|
||||
c.resources.dacs.1.commit_buffer();
|
||||
}
|
||||
|
||||
#[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])]
|
||||
|
|
|
|||
Loading…
Reference in New Issue