Updating QSPI frequency
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@ -462,7 +462,7 @@ const APP: () = {
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let qspi = hal::qspi::Qspi::bank2(
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dp.QUADSPI,
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qspi_pins,
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50.mhz(),
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40.mhz(),
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&ccdr.clocks,
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ccdr.peripheral.QSPI,
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);
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@ -576,8 +576,10 @@ const APP: () = {
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// IO_Update should be latched for 50ns after the QSPI profile write. Profile writes
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// are always 16 bytes, with 2 cycles required per byte, coming out to a total of 32
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// QSPI clock cycles. The QSPI is configured for 50MHz, so this comes out to an
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// offset of 640nS. We use 900ns to be safe.
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// QSPI clock cycles. The QSPI is configured for 40MHz, so this comes out to an
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// offset of 800nS. We use 900ns to be safe - note that the timer is triggered after
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// the QSPI write, which can take approximately 120nS, so there is additional
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// margin.
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hrtimer.configure_single_shot(
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hrtimer::Channel::Two,
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50_e-9,
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