Adding updated QSPI stream writer
parent
01a169ca69
commit
d93d0c7125
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@ -1,7 +1,7 @@
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#![no_std]
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use bit_field::BitField;
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use embedded_hal::{blocking::delay::DelayMs, digital::v2::OutputPin};
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use embedded_hal::{blocking::delay::DelayUs, digital::v2::OutputPin};
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/// A device driver for the AD9959 direct digital synthesis (DDS) chip.
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///
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@ -14,7 +14,7 @@ use embedded_hal::{blocking::delay::DelayMs, digital::v2::OutputPin};
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/// The chip supports a number of serial interfaces to improve data throughput, including normal,
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/// dual, and quad SPI configurations.
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pub struct Ad9959<INTERFACE> {
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pub interface: INTERFACE,
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interface: INTERFACE,
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reference_clock_frequency: f32,
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system_clock_multiplier: u8,
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communication_mode: Mode,
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@ -72,6 +72,7 @@ pub enum Register {
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}
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/// Specifies an output channel of the AD9959 DDS chip.
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#[derive(Copy, Clone, PartialEq)]
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pub enum Channel {
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One = 0,
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Two = 1,
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@ -103,9 +104,9 @@ impl<I: Interface> Ad9959<I> {
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/// `clock_frequency` to generate the system clock.
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pub fn new(
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interface: I,
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reset_pin: &mut impl OutputPin,
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mut reset_pin: impl OutputPin,
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io_update: &mut impl OutputPin,
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delay: &mut impl DelayMs<u8>,
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delay: &mut impl DelayUs<u8>,
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desired_mode: Mode,
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clock_frequency: f32,
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multiplier: u8,
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@ -124,8 +125,9 @@ impl<I: Interface> Ad9959<I> {
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io_update.set_low().or(Err(Error::Pin))?;
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// Delay for a clock cycle to allow the device to reset.
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delay.delay_ms((1000.0 / clock_frequency as f32) as u8);
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// Delay for at least 1 SYNC_CLK period for the reset to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK).
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delay.delay_us(5);
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reset_pin.set_low().or(Err(Error::Pin))?;
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@ -141,8 +143,11 @@ impl<I: Interface> Ad9959<I> {
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// Latch the new interface configuration.
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io_update.set_high().or(Err(Error::Pin))?;
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// Delay for a clock cycle to allow the device to reset.
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delay.delay_ms(2 * (1000.0 / clock_frequency as f32) as u8);
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// Delay for at least 1 SYNC_CLK period for the update to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK).
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delay.delay_us(5);
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io_update.set_low().or(Err(Error::Pin))?;
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ad9959
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@ -150,6 +155,13 @@ impl<I: Interface> Ad9959<I> {
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.configure_mode(desired_mode)
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.or(Err(Error::Interface))?;
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// Empirical evidence indicates a delay is necessary here for the IO update to become
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// active. This is likely due to needing to wait at least 1 clock cycle of the DDS for the
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// interface update to occur.
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// Delay for at least 1 SYNC_CLK period for the update to occur. The SYNC_CLK is guaranteed
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// to be at least 250KHz (1/4 of 1MHz minimum REF_CLK).
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delay.delay_us(5);
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// Read back the CSR to ensure it specifies the mode correctly.
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let mut updated_csr: [u8; 1] = [0];
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ad9959.read(Register::CSR, &mut updated_csr)?;
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@ -480,24 +492,96 @@ impl<I: Interface> Ad9959<I> {
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/ (1u64 << 32) as f32)
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}
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pub fn free(self) -> I {
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self.interface
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pub fn freeze(self) -> (I, DdsConfig) {
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let config = DdsConfig {
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mode: self.communication_mode,
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};
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(self.interface, config)
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}
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}
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struct ProfileSerializer {
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pub struct DdsConfig {
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mode: Mode,
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}
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impl DdsConfig {
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pub fn builder(&self) -> ProfileSerializer {
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ProfileSerializer::new(self.mode)
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}
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}
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pub struct ProfileSerializer {
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data: [u8; 16],
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index: usize,
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mode: Mode,
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}
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impl ProfileSerializer {
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fn new() -> Self {
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fn new(mode: Mode) -> Self {
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Self {
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mode,
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data: [0; 16],
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index: 0,
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}
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}
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pub fn update_channels(
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&mut self,
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channels: &[Channel],
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ftw: Option<u32>,
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pow: Option<u16>,
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acr: Option<u16>,
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) {
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// If there are no updates requested, skip this update cycle.
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if (ftw.is_none() && acr.is_none() && pow.is_none())
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|| channels.len() == 0
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{
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panic!("Invalid config");
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}
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let mut csr: u8 = *0u8.set_bits(1..3, self.mode as u8);
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for channel in channels.iter() {
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csr.set_bit(4 + *channel as usize, true);
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}
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self.add_write(Register::CSR, &[csr]);
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if let Some(ftw) = ftw {
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self.add_write(Register::CFTW0, &ftw.to_be_bytes());
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}
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if let Some(pow) = pow {
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self.add_write(Register::CPOW0, &pow.to_be_bytes());
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}
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if let Some(acr) = acr {
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self.add_write(Register::ACR, &acr.to_be_bytes());
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}
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}
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pub fn finalize<'a>(&'a mut self) -> &[u32] {
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//&self.data[..self.index]
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// Pad the buffer to 32-bit alignment by adding dummy writes to CSR and FR2.
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let padding = 4 - (self.index % 4);
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match padding {
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0 => {}
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1 => {
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// For a pad size of 1, we have to pad with 5 bytes to align things.
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self.add_write(Register::CSR, &[(self.mode as u8) << 1]);
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self.add_write(Register::FR2, &[0, 0, 0]);
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}
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2 => self.add_write(Register::CSR, &[(self.mode as u8) << 1]),
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3 => self.add_write(Register::FR2, &[0, 0, 0]),
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_ => panic!("Invalid"),
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}
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unsafe {
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core::slice::from_raw_parts::<'a, u32>(
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&self.data as *const _ as *const u32,
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self.index / 4,
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)
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}
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}
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fn add_write(&mut self, register: Register, value: &[u8]) {
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let data = &mut self.data[self.index..];
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assert!(value.len() + 1 <= data.len());
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@ -506,47 +590,4 @@ impl ProfileSerializer {
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data[1..][..value.len()].copy_from_slice(value);
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self.index += value.len() + 1;
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}
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fn finalize(self) -> [u32; 4] {
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assert!(self.index == self.data.len());
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unsafe { core::mem::transmute(self.data) }
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}
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}
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pub fn serialize_profile(
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channel: Channel,
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ftw: u32,
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pow: u16,
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acr: Option<u16>,
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) -> [u32; 4] {
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let mut serializer = ProfileSerializer::new();
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let csr: u8 = *0x00_u8
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.set_bits(1..=2, Mode::FourBitSerial as u8)
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.set_bit(4 + channel as usize, true);
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let acr: [u8; 3] = {
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let mut data = [0u8; 3];
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if acr.is_some() {
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data[2].set_bit(0, acr.is_some());
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data[0..2].copy_from_slice(&acr.unwrap().to_be_bytes());
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}
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data
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};
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// 4 bytes
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serializer.add_write(Register::CSR, &[csr]);
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serializer.add_write(Register::CSR, &[csr]);
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// 5 bytes
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serializer.add_write(Register::CFTW0, &ftw.to_be_bytes());
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// 3 bytes
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serializer.add_write(Register::CPOW0, &pow.to_be_bytes());
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// 4 bytes
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serializer.add_write(Register::ACR, &acr);
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serializer.finalize()
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}
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22
src/main.rs
22
src/main.rs
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@ -72,8 +72,8 @@ mod server;
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use adc::{Adc0Input, Adc1Input, AdcInputs};
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use dac::{Dac0Output, Dac1Output, DacOutputs};
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use pounder::DdsOutput;
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use dsp::iir;
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use pounder::DdsOutput;
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#[cfg(not(feature = "semihosting"))]
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fn init_log() {}
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@ -509,12 +509,12 @@ const APP: () = {
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pounder::QspiInterface::new(qspi).unwrap()
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};
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let mut reset_pin = gpioa.pa0.into_push_pull_output();
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let reset_pin = gpioa.pa0.into_push_pull_output();
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let mut io_update = gpiog.pg7.into_push_pull_output();
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let ad9959 = ad9959::Ad9959::new(
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qspi_interface,
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&mut reset_pin,
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reset_pin,
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&mut io_update,
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&mut delay,
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ad9959::Mode::FourBitSerial,
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@ -643,8 +643,9 @@ const APP: () = {
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hrtimer
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};
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let qspi = ad9959.free();
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DdsOutput::new(qspi, io_update_trigger)
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let (mut qspi, config) = ad9959.freeze();
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qspi.start_stream().unwrap();
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DdsOutput::new(qspi, io_update_trigger, config)
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};
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(Some(pounder_devices), Some(dds_output))
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@ -817,14 +818,13 @@ const APP: () = {
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}
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if let Some(dds_output) = c.resources.dds_output {
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let profile = ad9959::serialize_profile(
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pounder::Channel::Out0.into(),
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u32::MAX / 4,
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0,
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let builder = dds_output.builder().update_channels(
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&[pounder::Channel::Out0.into()],
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Some(u32::MAX / 4),
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None,
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None,
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);
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dds_output.write_profile(profile);
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builder.write_profile();
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}
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c.resources.dacs.commit_data();
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@ -1,42 +1,77 @@
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use super::QspiInterface;
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use crate::hrtimer::HighResTimerE;
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use ad9959::{Channel, DdsConfig, ProfileSerializer};
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use stm32h7xx_hal as hal;
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pub struct DdsOutput {
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_qspi: QspiInterface,
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io_update_trigger: HighResTimerE,
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config: DdsConfig,
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}
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impl DdsOutput {
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pub fn new(_qspi: QspiInterface, io_update_trigger: HighResTimerE) -> Self {
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pub fn new(
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_qspi: QspiInterface,
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io_update_trigger: HighResTimerE,
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dds_config: DdsConfig,
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) -> Self {
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Self {
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config: dds_config,
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_qspi,
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io_update_trigger,
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}
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}
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pub fn write_profile(&mut self, profile: [u32; 4]) {
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pub fn builder(&mut self) -> ProfileBuilder {
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let builder = self.config.builder();
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ProfileBuilder {
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dds_stream: self,
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serializer: builder,
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}
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}
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fn write_profile(&mut self, profile: &[u32]) {
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assert!(profile.len() <= 16);
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// Note(unsafe): We own the QSPI interface, so it is safe to access the registers in a raw
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// fashion.
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let regs = unsafe { &*hal::stm32::QUADSPI::ptr() };
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unsafe {
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[0],
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);
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[1],
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);
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[2],
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);
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[3],
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);
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for word in profile.iter() {
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// Note(unsafe): We are writing to the SPI TX FIFO in a raw manner for performance. This
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// is safe because we know the data register is a valid address to write to.
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unsafe {
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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*word,
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);
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}
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}
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// Trigger the IO_update signal generating timer to asynchronous create the IO_Update pulse.
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self.io_update_trigger.trigger();
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}
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}
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pub struct ProfileBuilder<'a> {
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dds_stream: &'a mut DdsOutput,
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serializer: ProfileSerializer,
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}
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impl<'a> ProfileBuilder<'a> {
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pub fn update_channels(
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mut self,
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channels: &[Channel],
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ftw: Option<u32>,
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pow: Option<u16>,
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acr: Option<u16>,
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) -> Self {
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self.serializer.update_channels(channels, ftw, pow, acr);
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self
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}
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pub fn write_profile(mut self) {
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let profile = self.serializer.finalize();
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self.dds_stream.write_profile(profile);
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}
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}
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@ -115,7 +115,7 @@ impl QspiInterface {
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})
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}
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fn start_stream(&mut self) -> Result<(), Error> {
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pub fn start_stream(&mut self) -> Result<(), Error> {
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if self.qspi.is_busy() {
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return Err(Error::Qspi);
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}
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@ -323,9 +323,6 @@ impl PounderDevices {
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.configure_system_clock(100_000_000f32, 4)
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.map_err(|_| Error::Dds)?;
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// Run the DDS in stream-only mode (no read support).
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ad9959.interface.start_stream().unwrap();
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Ok(devices)
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}
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}
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