pounder_test/src/main.rs

924 lines
34 KiB
Rust
Raw Normal View History

2020-06-09 00:17:51 +08:00
#![deny(warnings)]
#![allow(clippy::missing_safety_doc)]
2019-03-18 19:56:26 +08:00
#![no_std]
#![no_main]
2019-10-22 21:43:49 +08:00
#![cfg_attr(feature = "nightly", feature(asm))]
2019-03-18 19:56:26 +08:00
// Enable returning `!`
2019-10-22 21:43:49 +08:00
#![cfg_attr(feature = "nightly", feature(never_type))]
#![cfg_attr(feature = "nightly", feature(core_intrinsics))]
2019-03-18 19:56:26 +08:00
2019-06-07 17:26:24 +08:00
#[inline(never)]
#[panic_handler]
2019-10-22 21:43:49 +08:00
#[cfg(all(feature = "nightly", not(feature = "semihosting")))]
2019-06-07 17:26:24 +08:00
fn panic(_info: &core::panic::PanicInfo) -> ! {
2020-06-09 00:36:29 +08:00
let gpiod = unsafe { &*hal::stm32::GPIOD::ptr() };
2019-11-24 22:09:52 +08:00
gpiod.odr.modify(|_, w| w.odr6().high().odr12().high()); // FP_LED_1, FP_LED_3
unsafe {
core::intrinsics::abort();
}
2019-06-07 17:26:24 +08:00
}
2019-03-18 19:56:26 +08:00
#[cfg(feature = "semihosting")]
extern crate panic_semihosting;
2019-10-22 21:43:49 +08:00
#[cfg(not(any(feature = "nightly", feature = "semihosting")))]
extern crate panic_halt;
2019-03-18 19:56:26 +08:00
#[macro_use]
extern crate log;
2019-06-03 23:06:11 +08:00
// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
2020-06-16 22:22:12 +08:00
use cortex_m_rt::exception;
2020-06-17 18:20:45 +08:00
use rtic::cyccnt::{Instant, U32Ext};
2020-04-19 19:37:03 +08:00
use stm32h7xx_hal as hal;
2020-06-16 22:22:12 +08:00
use stm32h7xx_hal::prelude::*;
2020-04-19 19:37:03 +08:00
2020-06-21 20:30:49 +08:00
use embedded_hal::digital::v2::{InputPin, OutputPin};
2019-03-18 19:56:26 +08:00
use smoltcp as net;
2020-10-26 23:58:29 +08:00
use hal::{
ethernet,
dma::{DmaExt, DmaChannel, DmaInternal},
};
2020-06-16 22:22:12 +08:00
use heapless::{consts::*, String};
2020-06-09 01:13:55 +08:00
#[link_section = ".sram3.eth"]
static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
2019-05-24 00:57:00 +08:00
mod afe;
2019-11-24 22:09:52 +08:00
mod eeprom;
2020-06-09 01:13:55 +08:00
mod iir;
mod pounder;
2020-06-09 01:13:55 +08:00
mod server;
2019-09-05 07:54:00 +08:00
2019-03-18 19:56:26 +08:00
#[cfg(not(feature = "semihosting"))]
fn init_log() {}
#[cfg(feature = "semihosting")]
fn init_log() {
2019-11-24 22:09:52 +08:00
use cortex_m_log::log::{init as init_log, Logger};
use cortex_m_log::printer::semihosting::{hio::HStdout, InterruptOk};
2019-03-18 19:56:26 +08:00
use log::LevelFilter;
static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
let logger = Logger {
2019-04-13 00:13:18 +08:00
inner: InterruptOk::<_>::stdout().unwrap(),
2019-03-18 19:56:26 +08:00
level: LevelFilter::Info,
};
2019-11-24 22:09:52 +08:00
let logger = unsafe { LOGGER.get_or_insert(logger) };
2019-03-18 19:56:26 +08:00
2019-05-31 00:03:48 +08:00
init_log(logger).unwrap();
2019-03-18 19:56:26 +08:00
}
// Pull in build information (from `built` crate)
mod build_info {
#![allow(dead_code)]
2019-05-24 00:57:00 +08:00
// include!(concat!(env!("OUT_DIR"), "/built.rs"));
2019-03-18 19:56:26 +08:00
}
pub struct NetStorage {
ip_addrs: [net::wire::IpCidr; 1],
neighbor_cache: [Option<(net::wire::IpAddress, net::iface::Neighbor)>; 8],
}
static mut NET_STORE: NetStorage = NetStorage {
// Placeholder for the real IP address, which is initialized at runtime.
2020-06-16 22:22:12 +08:00
ip_addrs: [net::wire::IpCidr::Ipv6(
net::wire::Ipv6Cidr::SOLICITED_NODE_PREFIX,
)],
neighbor_cache: [None; 8],
};
2019-05-31 00:03:48 +08:00
const SCALE: f32 = ((1 << 15) - 1) as f32;
2019-03-25 17:08:27 +08:00
2020-06-08 15:36:28 +08:00
const SPI_START_CODE: u32 = 0x201;
2019-06-03 23:06:11 +08:00
// static ETHERNET_PENDING: AtomicBool = AtomicBool::new(true);
2019-04-30 19:42:05 +08:00
const TCP_RX_BUFFER_SIZE: usize = 8192;
const TCP_TX_BUFFER_SIZE: usize = 8192;
type AFE0 = afe::ProgrammableGainAmplifier<
hal::gpio::gpiof::PF2<hal::gpio::Output<hal::gpio::PushPull>>,
2020-06-16 22:22:12 +08:00
hal::gpio::gpiof::PF5<hal::gpio::Output<hal::gpio::PushPull>>,
>;
type AFE1 = afe::ProgrammableGainAmplifier<
hal::gpio::gpiod::PD14<hal::gpio::Output<hal::gpio::PushPull>>,
2020-06-16 22:22:12 +08:00
hal::gpio::gpiod::PD15<hal::gpio::Output<hal::gpio::PushPull>>,
>;
macro_rules! route_request {
2020-06-03 22:53:25 +08:00
($request:ident,
readable_attributes: [$($read_attribute:tt: $getter:tt),*],
modifiable_attributes: [$($write_attribute:tt: $TYPE:ty, $setter:tt),*]) => {
2020-06-09 20:16:01 +08:00
match $request.req {
server::AccessRequest::Read => {
match $request.attribute {
$(
2020-06-09 20:16:01 +08:00
$read_attribute => {
let value = match $getter() {
Ok(data) => data,
2020-06-09 20:16:01 +08:00
Err(_) => return server::Response::error($request.attribute,
2020-06-12 00:09:01 +08:00
"Failed to read attribute"),
};
let encoded_data: String<U256> = match serde_json_core::to_string(&value) {
Ok(data) => data,
2020-06-09 20:16:01 +08:00
Err(_) => return server::Response::error($request.attribute,
"Failed to encode attribute value"),
};
server::Response::success($request.attribute, &encoded_data)
},
)*
2020-06-09 20:16:01 +08:00
_ => server::Response::error($request.attribute, "Unknown attribute")
}
},
2020-06-09 20:16:01 +08:00
server::AccessRequest::Write => {
match $request.attribute {
$(
2020-06-09 20:16:01 +08:00
$write_attribute => {
let new_value = match serde_json_core::from_str::<$TYPE>(&$request.value) {
Ok(data) => data,
2020-06-09 20:16:01 +08:00
Err(_) => return server::Response::error($request.attribute,
"Failed to decode value"),
};
match $setter(new_value) {
Ok(_) => server::Response::success($request.attribute, &$request.value),
2020-06-09 20:16:01 +08:00
Err(_) => server::Response::error($request.attribute,
"Failed to set attribute"),
}
}
)*
2020-06-09 20:16:01 +08:00
_ => server::Response::error($request.attribute, "Unknown attribute")
}
}
}
}
}
2020-06-08 15:36:28 +08:00
2020-06-17 18:20:45 +08:00
#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
2019-05-31 00:03:48 +08:00
const APP: () = {
2019-08-26 21:47:42 +08:00
struct Resources {
2020-10-19 23:12:02 +08:00
adc0: hal::spi::Spi<hal::stm32::SPI2, hal::spi::Enabled, u16>,
dac0: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
afe0: AFE0,
2020-04-19 19:37:03 +08:00
2020-10-19 23:12:02 +08:00
adc1: hal::spi::Spi<hal::stm32::SPI3, hal::spi::Enabled, u16>,
dac1: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
afe1: AFE1,
2020-04-19 19:37:03 +08:00
eeprom_i2c: hal::i2c::I2c<hal::stm32::I2C2>,
2020-04-19 19:37:03 +08:00
timer: hal::timer::Timer<hal::stm32::TIM2>,
2020-06-21 20:39:23 +08:00
2020-06-21 19:36:45 +08:00
// Note: It appears that rustfmt generates a format that GDB cannot recognize, which
// results in GDB breakpoints being set improperly. To debug, redefine the following
// definition to:
//
// ```rust
// net_interface: net::iface::EthernetInterface<
// 'static,
// 'static,
// 'static,
// ethernet::EthernetDMA<'static>>,
// ```
2020-06-16 22:22:12 +08:00
net_interface: net::iface::EthernetInterface<
'static,
'static,
'static,
2020-06-21 19:36:45 +08:00
ethernet::EthernetDMA<'static>,
>,
2020-06-09 20:16:01 +08:00
eth_mac: ethernet::EthernetMAC,
mac_addr: net::wire::EthernetAddress,
2020-06-20 22:43:07 +08:00
pounder: Option<pounder::PounderDevices<asm_delay::AsmDelay>>,
2020-06-09 00:20:10 +08:00
2019-08-26 21:47:42 +08:00
#[init([[0.; 5]; 2])]
2020-06-09 01:13:55 +08:00
iir_state: [iir::IIRState; 2],
#[init([iir::IIR { ba: [1., 0., 0., 0., 0.], y_offset: 0., y_min: -SCALE - 1., y_max: SCALE }; 2])]
iir_ch: [iir::IIR; 2],
2019-08-26 21:47:42 +08:00
}
2019-05-31 00:03:48 +08:00
#[init]
2019-05-31 00:03:48 +08:00
fn init(c: init::Context) -> init::LateResources {
2020-04-19 19:37:03 +08:00
let dp = c.device;
let mut cp = c.core;
2020-04-19 19:37:03 +08:00
let pwr = dp.PWR.constrain();
let vos = pwr.freeze();
2020-10-19 23:12:02 +08:00
// Enable SRAM3 for the ethernet descriptor ring.
dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
// Clear reset flags.
dp.RCC.rsr.write(|w| w.rmvf().set_bit());
// Select the PLLs for SPI.
dp.RCC
.d2ccip1r
.modify(|_, w| w.spi123sel().pll2_p().spi45sel().pll2_q());
2020-04-19 19:37:03 +08:00
let rcc = dp.RCC.constrain();
2020-10-19 23:12:02 +08:00
let clocks = rcc
2020-06-21 20:39:23 +08:00
.use_hse(8.mhz())
2020-04-19 19:37:03 +08:00
.sysclk(400.mhz())
.hclk(200.mhz())
.per_ck(100.mhz())
.pll2_p_ck(100.mhz())
.pll2_q_ck(100.mhz())
.freeze(vos, &dp.SYSCFG);
2020-06-09 20:16:49 +08:00
init_log();
2020-06-09 00:20:10 +08:00
let mut delay = hal::delay::Delay::new(cp.SYST, clocks.clocks);
2020-10-19 23:12:02 +08:00
let gpioa = dp.GPIOA.split(clocks.peripheral.GPIOA);
let gpiob = dp.GPIOB.split(clocks.peripheral.GPIOB);
let gpioc = dp.GPIOC.split(clocks.peripheral.GPIOC);
let gpiod = dp.GPIOD.split(clocks.peripheral.GPIOD);
let gpioe = dp.GPIOE.split(clocks.peripheral.GPIOE);
let gpiof = dp.GPIOF.split(clocks.peripheral.GPIOF);
let gpiog = dp.GPIOG.split(clocks.peripheral.GPIOG);
2020-04-19 19:37:03 +08:00
let afe0 = {
let a0_pin = gpiof.pf2.into_push_pull_output();
let a1_pin = gpiof.pf5.into_push_pull_output();
afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
};
let afe1 = {
let a0_pin = gpiod.pd14.into_push_pull_output();
let a1_pin = gpiod.pd15.into_push_pull_output();
afe::ProgrammableGainAmplifier::new(a0_pin, a1_pin)
};
2020-10-26 23:58:29 +08:00
let mut dma_channels = dp.DMA1.split();
2020-04-19 19:37:03 +08:00
// Configure the SPI interfaces to the ADCs and DACs.
let adc0_spi = {
2020-06-16 22:22:12 +08:00
let spi_miso = gpiob
.pb14
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpiob
.pb10
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
2020-06-23 04:55:18 +08:00
let _spi_nss = gpiob
.pb9
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
2020-04-19 19:37:03 +08:00
2020-06-16 22:22:12 +08:00
let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
})
.manage_cs()
.cs_delay(220e-9);
2020-04-22 01:02:52 +08:00
2020-10-26 23:58:29 +08:00
dma_channels.0.set_peripheral_address(&dp.SPI2.cr1 as *const _ as u32, false);
dma_channels.0.set_memory_address(&SPI_START_CODE as *const _ as u32, false);
dma_channels.0.set_direction(hal::dma::Direction::MemoryToPeripherial);
dma_channels.0.set_transfer_length(1);
dma_channels.0.cr().modify(|_, w| w.circ().enabled());
dma_channels.0.dmamux().modify(|_, w|
w.dmareq_id().variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP));
dma_channels.0.start();
2020-10-19 23:12:02 +08:00
let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI2.spi(
2020-06-16 22:22:12 +08:00
(spi_sck, spi_miso, hal::spi::NoMosi),
config,
50.mhz(),
2020-10-19 23:12:02 +08:00
clocks.peripheral.SPI2,
&clocks.clocks,
2020-06-16 22:22:12 +08:00
);
2020-04-19 19:37:03 +08:00
2020-10-26 23:58:29 +08:00
spi.listen(hal::spi::Event::Rxp);
2020-04-19 19:37:03 +08:00
spi
2020-04-19 19:37:03 +08:00
};
let adc1_spi = {
2020-06-16 22:22:12 +08:00
let spi_miso = gpiob
.pb4
.into_alternate_af6()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpioc
.pc10
.into_alternate_af6()
.set_speed(hal::gpio::Speed::VeryHigh);
2020-06-23 04:55:18 +08:00
let _spi_nss = gpioa
.pa15
.into_alternate_af6()
.set_speed(hal::gpio::Speed::VeryHigh);
2020-04-19 19:37:03 +08:00
2020-06-16 22:22:12 +08:00
let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
})
.manage_cs()
.cs_delay(220e-9);
2020-04-22 01:02:52 +08:00
2020-10-26 23:58:29 +08:00
dma_channels.1.set_peripheral_address(&dp.SPI3.cr1 as *const _ as u32, false);
dma_channels.1.set_memory_address(&SPI_START_CODE as *const _ as u32, false);
dma_channels.1.set_direction(hal::dma::Direction::MemoryToPeripherial);
dma_channels.1.dmamux().modify(|_, w|
w.dmareq_id().variant(hal::stm32::dmamux1::ccr::DMAREQ_ID_A::TIM2_UP));
dma_channels.1.set_transfer_length(1);
dma_channels.1.cr().modify(|_, w| w.circ().enabled());
dma_channels.1.start();
2020-10-19 23:12:02 +08:00
let mut spi: hal::spi::Spi<_, _, u16> = dp.SPI3.spi(
2020-06-16 22:22:12 +08:00
(spi_sck, spi_miso, hal::spi::NoMosi),
config,
50.mhz(),
2020-10-19 23:12:02 +08:00
clocks.peripheral.SPI3,
&clocks.clocks,
2020-06-16 22:22:12 +08:00
);
2020-04-19 19:37:03 +08:00
2020-10-26 23:58:29 +08:00
spi.listen(hal::spi::Event::Rxp);
spi
2020-04-19 19:37:03 +08:00
};
2020-06-23 20:16:33 +08:00
let _dac_clr_n = gpioe.pe12.into_push_pull_output().set_high().unwrap();
2020-06-23 20:55:59 +08:00
let _dac0_ldac_n =
gpioe.pe11.into_push_pull_output().set_low().unwrap();
let _dac1_ldac_n =
gpioe.pe15.into_push_pull_output().set_low().unwrap();
2020-06-23 20:13:55 +08:00
let dac0_spi = {
2020-06-16 22:22:12 +08:00
let spi_miso = gpioe
.pe5
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpioe
.pe2
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
2020-06-23 04:55:18 +08:00
let _spi_nss = gpioe
.pe4
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
2020-04-19 19:37:03 +08:00
2020-06-16 22:22:12 +08:00
let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
})
.manage_cs()
.swap_mosi_miso();
dp.SPI4.spi(
2020-06-16 22:22:12 +08:00
(spi_sck, spi_miso, hal::spi::NoMosi),
config,
50.mhz(),
2020-10-19 23:12:02 +08:00
clocks.peripheral.SPI4,
&clocks.clocks,
)
2020-04-19 19:37:03 +08:00
};
let dac1_spi = {
2020-06-16 22:22:12 +08:00
let spi_miso = gpiof
.pf8
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpiof
.pf7
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
2020-06-23 04:55:18 +08:00
let _spi_nss = gpiof
.pf6
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
2020-04-19 19:37:03 +08:00
2020-06-16 22:22:12 +08:00
let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
})
.manage_cs()
.swap_mosi_miso();
dp.SPI5.spi(
2020-06-16 22:22:12 +08:00
(spi_sck, spi_miso, hal::spi::NoMosi),
config,
50.mhz(),
2020-10-19 23:12:02 +08:00
clocks.peripheral.SPI5,
&clocks.clocks,
)
};
2020-04-19 19:37:03 +08:00
let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
let mut fp_led_1 = gpiod.pd6.into_push_pull_output();
let mut fp_led_2 = gpiog.pg4.into_push_pull_output();
let mut fp_led_3 = gpiod.pd12.into_push_pull_output();
fp_led_0.set_low().unwrap();
fp_led_1.set_low().unwrap();
fp_led_2.set_low().unwrap();
fp_led_3.set_low().unwrap();
2020-06-21 20:30:49 +08:00
// Measure the Pounder PGOOD output to detect if pounder is present on Stabilizer.
let pounder_pgood = gpiob.pb13.into_pull_down_input();
delay.delay_ms(2u8);
let pounder_devices = if pounder_pgood.is_high().unwrap() {
2020-06-16 22:22:12 +08:00
let ad9959 = {
2020-06-09 00:20:10 +08:00
let qspi_interface = {
// Instantiate the QUADSPI pins and peripheral interface.
2020-10-19 23:12:02 +08:00
let qspi_pins = {
let _qspi_ncs = gpioc
.pc11
.into_alternate_af9()
.set_speed(hal::gpio::Speed::VeryHigh);
let clk = gpiob
.pb2
.into_alternate_af9()
.set_speed(hal::gpio::Speed::VeryHigh);
let io0 = gpioe
.pe7
.into_alternate_af10()
.set_speed(hal::gpio::Speed::VeryHigh);
let io1 = gpioe
.pe8
.into_alternate_af10()
.set_speed(hal::gpio::Speed::VeryHigh);
let io2 = gpioe
.pe9
.into_alternate_af10()
.set_speed(hal::gpio::Speed::VeryHigh);
let io3 = gpioe
.pe10
.into_alternate_af10()
.set_speed(hal::gpio::Speed::VeryHigh);
(clk, io0, io1, io2, io3)
};
let qspi = hal::qspi::Qspi::bank2(dp.QUADSPI, qspi_pins, 11.mhz(), &clocks.clocks,
clocks.peripheral.QSPI);
2020-06-09 00:20:10 +08:00
pounder::QspiInterface::new(qspi).unwrap()
};
let mut reset_pin = gpioa.pa0.into_push_pull_output();
let io_update = gpiog.pg7.into_push_pull_output();
let asm_delay = {
let frequency_hz = clocks.clocks.c_ck().0;
2020-06-16 22:22:12 +08:00
asm_delay::AsmDelay::new(asm_delay::bitrate::Hertz(
frequency_hz,
))
2020-06-09 00:20:10 +08:00
};
2020-06-16 22:22:12 +08:00
ad9959::Ad9959::new(
qspi_interface,
&mut reset_pin,
io_update,
asm_delay,
ad9959::Mode::FourBitSerial,
100_000_000f32,
5,
)
.unwrap()
2020-06-09 00:20:10 +08:00
};
2020-06-21 20:30:49 +08:00
let io_expander = {
let sda = gpiob.pb7.into_alternate_af4().set_open_drain();
let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
2020-10-19 23:12:02 +08:00
let i2c1 = dp.I2C1.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C1, &clocks.clocks);
2020-06-21 20:30:49 +08:00
mcp23017::MCP23017::default(i2c1).unwrap()
};
2020-06-09 00:20:10 +08:00
let spi = {
2020-06-16 22:22:12 +08:00
let spi_mosi = gpiod
.pd7
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_miso = gpioa
.pa6
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let spi_sck = gpiog
.pg11
.into_alternate_af5()
.set_speed(hal::gpio::Speed::VeryHigh);
let config = hal::spi::Config::new(hal::spi::Mode {
polarity: hal::spi::Polarity::IdleHigh,
phase: hal::spi::Phase::CaptureOnSecondTransition,
2020-10-19 23:12:02 +08:00
});
2020-06-09 00:20:10 +08:00
// The maximum frequency of this SPI must be limited due to capacitance on the MISO
// line causing a long RC decay.
2020-06-16 22:22:12 +08:00
dp.SPI1.spi(
(spi_sck, spi_miso, spi_mosi),
config,
5.mhz(),
2020-10-19 23:12:02 +08:00
clocks.peripheral.SPI1,
&clocks.clocks,
2020-06-16 22:22:12 +08:00
)
2020-06-09 00:20:10 +08:00
};
2020-10-19 23:12:02 +08:00
let (adc1, adc2) = {
let (mut adc1, mut adc2) = hal::adc::adc12(dp.ADC1, dp.ADC2, &mut delay, clocks.peripheral.ADC12, &clocks.clocks);
2020-06-09 00:20:10 +08:00
2020-10-19 23:12:02 +08:00
let adc1 = {
adc1.calibrate();
adc1.enable()
};
2020-06-09 00:20:10 +08:00
2020-10-19 23:12:02 +08:00
let adc2 = {
adc2.calibrate();
adc2.enable()
};
2020-06-09 00:20:10 +08:00
2020-10-19 23:12:02 +08:00
(adc1, adc2)
2020-06-09 00:20:10 +08:00
};
let adc1_in_p = gpiof.pf11.into_analog();
let adc2_in_p = gpiof.pf14.into_analog();
2020-06-20 22:43:07 +08:00
Some(
pounder::PounderDevices::new(
io_expander,
ad9959,
spi,
adc1,
adc2,
adc1_in_p,
adc2_in_p,
)
.unwrap(),
2020-06-16 22:22:12 +08:00
)
2020-06-20 22:43:07 +08:00
} else {
None
2020-06-09 00:20:10 +08:00
};
let mut eeprom_i2c = {
2020-04-19 19:37:03 +08:00
let sda = gpiof.pf0.into_alternate_af4().set_open_drain();
let scl = gpiof.pf1.into_alternate_af4().set_open_drain();
2020-10-19 23:12:02 +08:00
dp.I2C2.i2c((scl, sda), 100.khz(), clocks.peripheral.I2C2, &clocks.clocks)
2020-04-19 19:37:03 +08:00
};
// Configure ethernet pins.
{
// Reset the PHY before configuring pins.
2020-10-19 23:12:02 +08:00
//let mut eth_phy_nrst = gpioe.pe3.into_push_pull_output();
//eth_phy_nrst.set_low().unwrap();
//delay.delay_ms(200u8);
//eth_phy_nrst.set_high().unwrap();
2020-06-16 22:22:12 +08:00
let _rmii_ref_clk = gpioa
.pa1
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_mdio = gpioa
.pa2
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_mdc = gpioc
.pc1
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_crs_dv = gpioa
.pa7
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_rxd0 = gpioc
.pc4
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_rxd1 = gpioc
.pc5
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_tx_en = gpiob
.pb11
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_txd0 = gpiob
.pb12
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
let _rmii_txd1 = gpiog
.pg14
.into_alternate_af11()
.set_speed(hal::gpio::Speed::VeryHigh);
}
let mac_addr = match eeprom::read_eui48(&mut eeprom_i2c) {
Err(_) => {
info!("Could not read EEPROM, using default MAC address");
net::wire::EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00])
}
Ok(raw_mac) => net::wire::EthernetAddress(raw_mac),
};
2020-04-22 01:02:52 +08:00
let (network_interface, eth_mac) = {
// Configure the ethernet controller
2020-10-19 23:12:02 +08:00
let (eth_dma, mut eth_mac) = unsafe {
ethernet::new_unchecked(
2020-06-16 22:22:12 +08:00
dp.ETHERNET_MAC,
dp.ETHERNET_MTL,
dp.ETHERNET_DMA,
&mut DES_RING,
mac_addr.clone(),
)
};
2020-10-19 23:12:02 +08:00
eth_mac.block_until_link();
2020-06-09 20:16:01 +08:00
unsafe { ethernet::enable_interrupt() };
let store = unsafe { &mut NET_STORE };
2020-06-16 22:22:12 +08:00
store.ip_addrs[0] = net::wire::IpCidr::new(
net::wire::IpAddress::v4(10, 0, 16, 99),
24,
);
2020-06-16 22:22:12 +08:00
let neighbor_cache =
net::iface::NeighborCache::new(&mut store.neighbor_cache[..]);
let interface = net::iface::EthernetInterfaceBuilder::new(eth_dma)
2020-06-16 22:22:12 +08:00
.ethernet_addr(mac_addr)
.neighbor_cache(neighbor_cache)
.ip_addrs(&mut store.ip_addrs[..])
.finalize();
(interface, eth_mac)
};
2020-04-19 19:37:03 +08:00
cp.SCB.enable_icache();
2019-05-31 00:03:48 +08:00
// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
// info!("Built on {}", build_info::BUILT_TIME_UTC);
// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
2020-06-17 18:20:45 +08:00
// Utilize the cycle counter for RTIC scheduling.
cp.DWT.enable_cycle_counter();
// Configure timer 2 to trigger conversions for the ADC
2020-10-26 23:58:29 +08:00
let timer2 = dp.TIM2.timer(500.khz(), clocks.peripheral.TIM2, &clocks.clocks);
{
let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() };
t2_regs.dier.modify(|_, w| w.ude().set_bit());
}
2020-06-08 15:36:28 +08:00
2019-05-31 04:57:41 +08:00
init::LateResources {
afe0: afe0,
adc0: adc0_spi,
dac0: dac0_spi,
afe1: afe1,
2020-04-19 19:37:03 +08:00
adc1: adc1_spi,
dac1: dac1_spi,
timer: timer2,
2020-06-09 00:20:10 +08:00
pounder: pounder_devices,
eeprom_i2c,
net_interface: network_interface,
eth_mac,
mac_addr,
2019-05-31 04:57:41 +08:00
}
}
#[task(binds = SPI3, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)]
fn spi3(c: spi3::Context) {
let output: u16 = {
let a: u16 = c.resources.adc1.read().unwrap();
let x0 = f32::from(a as i16);
2020-06-16 22:22:12 +08:00
let y0 =
c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
y0 as i16 as u16 ^ 0x8000
};
c.resources.dac1.send(output).unwrap();
}
#[task(binds = SPI2, resources = [adc0, dac0, iir_state, iir_ch], priority = 2)]
fn spi2(c: spi2::Context) {
let output: u16 = {
let a: u16 = c.resources.adc0.read().unwrap();
let x0 = f32::from(a as i16);
2020-06-16 22:22:12 +08:00
let y0 =
c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
y0 as i16 as u16 ^ 0x8000
};
c.resources.dac0.send(output).unwrap();
}
#[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])]
fn idle(mut c: idle::Context) -> ! {
let mut socket_set_entries: [_; 8] = Default::default();
2020-06-16 22:22:12 +08:00
let mut sockets =
net::socket::SocketSet::new(&mut socket_set_entries[..]);
let mut rx_storage = [0; TCP_RX_BUFFER_SIZE];
let mut tx_storage = [0; TCP_TX_BUFFER_SIZE];
2020-06-09 01:13:55 +08:00
let tcp_handle = {
2020-06-16 22:22:12 +08:00
let tcp_rx_buffer =
net::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
let tcp_tx_buffer =
net::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
let tcp_socket =
net::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
sockets.add(tcp_socket)
};
2020-04-29 01:26:43 +08:00
let mut server = server::Server::new();
2020-04-29 01:15:00 +08:00
let mut time = 0u32;
let mut next_ms = Instant::now();
// TODO: Replace with reference to CPU clock from CCDR.
next_ms += 400_000.cycles();
loop {
let tick = Instant::now() > next_ms;
if tick {
next_ms += 400_000.cycles();
time += 1;
}
2019-05-31 04:57:41 +08:00
{
2019-11-24 22:09:52 +08:00
let socket =
2020-06-09 01:13:55 +08:00
&mut *sockets.get::<net::socket::TcpSocket>(tcp_handle);
2019-06-03 23:06:11 +08:00
if socket.state() == net::socket::TcpState::CloseWait {
socket.close();
} else if !(socket.is_open() || socket.is_listening()) {
2019-11-24 22:09:52 +08:00
socket
.listen(1235)
.unwrap_or_else(|e| warn!("TCP listen error: {:?}", e));
2019-05-31 04:57:41 +08:00
} else {
server.poll(socket, |req| {
info!("Got request: {:?}", req);
2020-06-03 22:53:25 +08:00
route_request!(req,
readable_attributes: [
"stabilizer/iir/state": (|| {
2020-06-03 23:04:09 +08:00
let state = c.resources.iir_state.lock(|iir_state|
server::Status {
t: time,
x0: iir_state[0][0],
y0: iir_state[0][2],
x1: iir_state[1][0],
y1: iir_state[1][2],
});
Ok::<server::Status, ()>(state)
}),
"stabilizer/afe0/gain": (|| c.resources.afe0.get_gain()),
"stabilizer/afe1/gain": (|| c.resources.afe1.get_gain()),
"pounder/in0": (|| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) =>
pounder.get_input_channel_state(pounder::Channel::In0),
_ => Err(pounder::Error::Access),
}
}),
"pounder/in1": (|| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) =>
pounder.get_input_channel_state(pounder::Channel::In1),
_ => Err(pounder::Error::Access),
}
}),
"pounder/out0": (|| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) =>
pounder.get_output_channel_state(pounder::Channel::Out0),
_ => Err(pounder::Error::Access),
}
}),
"pounder/out1": (|| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) =>
pounder.get_output_channel_state(pounder::Channel::Out1),
_ => Err(pounder::Error::Access),
}
}),
"pounder/dds/clock": (|| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) => pounder.get_dds_clock_config(),
_ => Err(pounder::Error::Access),
}
})
],
2020-06-03 23:04:09 +08:00
modifiable_attributes: [
"stabilizer/iir0/state": server::IirRequest, (|req: server::IirRequest| {
2020-06-03 23:15:57 +08:00
c.resources.iir_ch.lock(|iir_ch| {
if req.channel > 1 {
return Err(());
}
iir_ch[req.channel as usize] = req.iir;
Ok::<server::IirRequest, ()>(req)
})
}),
"stabilizer/iir1/state": server::IirRequest, (|req: server::IirRequest| {
2020-06-03 23:15:57 +08:00
c.resources.iir_ch.lock(|iir_ch| {
if req.channel > 1 {
return Err(());
}
iir_ch[req.channel as usize] = req.iir;
Ok::<server::IirRequest, ()>(req)
})
}),
"pounder/in0": pounder::ChannelState, (|state| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) =>
pounder.set_channel_state(pounder::Channel::In0, state),
_ => Err(pounder::Error::Access),
}
}),
"pounder/in1": pounder::ChannelState, (|state| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) =>
pounder.set_channel_state(pounder::Channel::In1, state),
_ => Err(pounder::Error::Access),
}
}),
"pounder/out0": pounder::ChannelState, (|state| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) =>
pounder.set_channel_state(pounder::Channel::Out0, state),
_ => Err(pounder::Error::Access),
}
}),
"pounder/out1": pounder::ChannelState, (|state| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) =>
pounder.set_channel_state(pounder::Channel::Out1, state),
_ => Err(pounder::Error::Access),
}
}),
"pounder/dds/clock": pounder::DdsClockConfig, (|config| {
2020-06-20 22:43:07 +08:00
match c.resources.pounder {
Some(pounder) => pounder.configure_dds_clock(config),
_ => Err(pounder::Error::Access),
}
}),
"stabilizer/afe0/gain": afe::Gain, (|gain| {
Ok::<(), ()>(c.resources.afe0.set_gain(gain))
}),
"stabilizer/afe1/gain": afe::Gain, (|gain| {
2020-06-03 23:04:09 +08:00
Ok::<(), ()>(c.resources.afe1.set_gain(gain))
})
]
)
2019-06-03 23:06:11 +08:00
});
2019-05-31 04:57:41 +08:00
}
}
2020-06-16 22:22:12 +08:00
let sleep = match c.resources.net_interface.poll(
&mut sockets,
net::time::Instant::from_millis(time as i64),
) {
2020-06-09 20:16:01 +08:00
Ok(changed) => changed == false,
2019-05-31 04:57:41 +08:00
Err(net::Error::Unrecognized) => true,
2019-11-24 22:09:52 +08:00
Err(e) => {
info!("iface poll error: {:?}", e);
true
}
2020-04-29 01:15:00 +08:00
};
if sleep {
cortex_m::asm::wfi();
2019-05-31 04:57:41 +08:00
}
2019-05-31 00:03:48 +08:00
}
}
2019-04-28 19:37:14 +08:00
2020-06-09 20:16:01 +08:00
#[task(binds = ETH, priority = 1)]
fn eth(_: eth::Context) {
unsafe { ethernet::interrupt_handler() }
2019-05-31 00:03:48 +08:00
}
extern "C" {
2020-06-17 18:20:45 +08:00
// hw interrupt handlers for RTIC to use for scheduling tasks
2019-05-31 04:57:41 +08:00
// one per priority
2019-05-31 00:03:48 +08:00
fn DCMI();
fn JPEG();
fn SDMMC();
}
};
2019-03-18 19:56:26 +08:00
#[exception]
fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
panic!("HardFault at {:#?}", ef);
}
#[exception]
fn DefaultHandler(irqn: i16) {
panic!("Unhandled exception (IRQn = {})", irqn);
}