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pounder_test
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Adding WIP updates

master
Ryan Summers 2020-11-03 10:52:37 +01:00
parent 4e5459433e
commit e95cad5bde
3 changed files with 56 additions and 30 deletions
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5
src/adc.rs
View File

@ -1,9 +1,8 @@
use super::{
hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Stream,
TargetAddress, Transfer,
hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, TargetAddress, Transfer,
};
const INPUT_BUFFER_SIZE: usize = 1;
const INPUT_BUFFER_SIZE: usize = 25;
#[link_section = ".axisram.buffers"]
static mut SPI_START: [u16; 1] = [0x00];

23
src/dac.rs
View File

@ -4,27 +4,37 @@ use heapless::consts;
pub struct Dac0Output {
outputs: heapless::spsc::Queue<u16, consts::U32>,
spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
timer: hal::timer::Timer<hal::stm32::TIM3>,
}
impl Dac0Output {
pub fn new(
spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
mut timer: hal::timer::Timer<hal::stm32::TIM3>,
) -> Self {
spi.inner().cr1.modify(|_, w| w.cstart().started());
timer.pause();
timer.reset_counter();
timer.clear_irq();
timer.listen(hal::timer::Event::TimeOut);
Self {
spi,
outputs: heapless::spsc::Queue::new(),
timer,
}
}
pub fn push(&mut self, value: u16) {
self.outputs.enqueue(value).unwrap();
self.timer.resume();
}
pub fn update(&mut self) {
self.timer.clear_irq();
match self.outputs.dequeue() {
Some(value) => self.write(value),
None => {}
None => self.timer.pause(),
}
}
@ -41,28 +51,37 @@ impl Dac0Output {
pub struct Dac1Output {
outputs: heapless::spsc::Queue<u16, consts::U32>,
spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
timer: hal::timer::Timer<hal::stm32::TIM4>,
}
impl Dac1Output {
pub fn new(
spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
mut timer: hal::timer::Timer<hal::stm32::TIM4>,
) -> Self {
spi.inner().cr1.modify(|_, w| w.cstart().started());
timer.pause();
timer.reset_counter();
timer.clear_irq();
timer.listen(hal::timer::Event::TimeOut);
Self {
spi,
outputs: heapless::spsc::Queue::new(),
timer,
}
}
pub fn push(&mut self, value: u16) {
self.outputs.enqueue(value).unwrap();
self.timer.resume();
}
pub fn update(&mut self) {
self.timer.clear_irq();
match self.outputs.dequeue() {
Some(value) => self.write(value),
None => {}
None => self.timer.pause(),
}
}

58
src/main.rs
View File

@ -37,7 +37,7 @@ use embedded_hal::digital::v2::{InputPin, OutputPin};
use hal::{
dma::{
dma::{DMAReq, DmaConfig},
traits::{Stream, TargetAddress},
traits::TargetAddress,
MemoryToPeripheral, PeripheralToMemory, Transfer,
},
ethernet::{self, PHY},
@ -46,6 +46,8 @@ use smoltcp as net;
use heapless::{consts::*, String};
const SAMPLE_FREQUENCY_KHZ: u32 = 800;
#[link_section = ".sram3.eth"]
static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
@ -362,7 +364,8 @@ const APP: () = {
)
};
Dac0Output::new(dac0_spi)
let timer = dp.TIM3.timer(SAMPLE_FREQUENCY_KHZ.khz(), ccdr.peripheral.TIM3, &ccdr.clocks);
Dac0Output::new(dac0_spi, timer)
};
let dac1 = {
@ -398,7 +401,8 @@ const APP: () = {
)
};
Dac1Output::new(dac1_spi)
let timer = dp.TIM4.timer(SAMPLE_FREQUENCY_KHZ.khz(), ccdr.peripheral.TIM4, &ccdr.clocks);
Dac1Output::new(dac1_spi, timer)
};
let mut fp_led_0 = gpiod.pd5.into_push_pull_output();
@ -679,7 +683,7 @@ const APP: () = {
// Configure timer 2 to trigger conversions for the ADC
let timer2 =
dp.TIM2.timer(50.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
dp.TIM2.timer(SAMPLE_FREQUENCY_KHZ.khz(), ccdr.peripheral.TIM2, &ccdr.clocks);
{
let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() };
t2_regs.dier.modify(|_, w| w.ude().set_bit());
@ -704,36 +708,30 @@ const APP: () = {
}
}
#[task(binds=DMA1_STR3, resources=[adc1, dac1, iir_state, iir_ch], priority=2)]
fn adc1(c: adc1::Context) {
let samples = c.resources.adc1.transfer_complete_handler();
let mut last_result: u16 = 0;
for sample in samples {
let x0 = f32::from(*sample as i16);
let y0 =
c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
last_result = y0 as i16 as u16 ^ 0x8000;
//c.resources.dac0.push(last_result);
}
c.resources.dac1.write(last_result);
}
#[task(binds=DMA1_STR1, resources=[adc0, dac0, iir_state, iir_ch], priority=2)]
fn adc0(c: adc0::Context) {
fn adc0(mut c: adc0::Context) {
let samples = c.resources.adc0.transfer_complete_handler();
let mut last_result: u16 = 0;
for sample in samples {
let x0 = f32::from(*sample as i16);
let y0 =
c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
last_result = y0 as i16 as u16 ^ 0x8000;
//c.resources.dac0.push(last_result);
let result = y0 as i16 as u16 ^ 0x8000;
c.resources.dac0.lock(|dac| dac.push(result));
}
}
c.resources.dac0.write(last_result);
#[task(binds=DMA1_STR3, resources=[adc1, dac1, iir_state, iir_ch], priority=2)]
fn adc1(mut c: adc1::Context) {
let samples = c.resources.adc1.transfer_complete_handler();
for sample in samples {
let x0 = f32::from(*sample as i16);
let y0 =
c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
let result = y0 as i16 as u16 ^ 0x8000;
c.resources.dac1.lock(|dac| dac.push(result));
}
}
#[idle(resources=[net_interface, pounder, mac_addr, eth_mac, iir_state, iir_ch, afe0, afe1])]
@ -936,6 +934,16 @@ const APP: () = {
panic!("ADC0 input overrun");
}
#[task(binds = TIM3, resources=[dac0], priority = 3)]
fn dac0(c: dac0::Context) {
c.resources.dac0.update();
}
#[task(binds = TIM4, resources=[dac1], priority = 3)]
fn dac1(c: dac1::Context) {
c.resources.dac1.update();
}
extern "C" {
// hw interrupt handlers for RTIC to use for scheduling tasks
// one per priority