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a63fd306af
|
urukul: use spi2
* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
|
2018-02-21 15:00:28 +00:00 |
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37a0d6580b
|
spi2: add RTIO gateware and coredevice driver
1006218997
|
2018-02-21 13:37:36 +00:00 |
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91a4a7b0ee
|
kasli: free run si5324 on opticlock for now
|
2018-02-21 13:37:29 +00:00 |
|
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7a1d71502a
|
ttl_serdes_7series: drive IBUF and INTERM disables from serdes
|
2018-02-21 13:37:29 +00:00 |
|
|
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476e4fdd56
|
ttl_serdes_7series: disable IBUF and INTERM when output
|
2018-02-21 13:37:29 +00:00 |
|
Florent Kermarrec
|
afc16a67b6
|
firmware/liboard/sdram.rs: iterate read multiple times in read_delays to avoid false positives
|
2018-02-21 14:15:35 +01:00 |
|
whitequark
|
86ceee570f
|
compiler: reject calls with unexpected keyword arguments.
Fixes #924.
|
2018-02-21 11:37:12 +00:00 |
|
|
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f060d6e1b3
|
drtio: increase A7 clock aligner check period
|
2018-02-20 18:50:35 +08:00 |
|
|
|
738654c783
|
drtio: support remote RTIO resets
|
2018-02-20 18:48:54 +08:00 |
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f15b4bdde7
|
style
|
2018-02-20 18:47:59 +08:00 |
|
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7d9c7ada71
|
drtio: fix test infinite loop
|
2018-02-20 17:42:00 +08:00 |
|
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ad2c9590d0
|
drtio: rewrite/fix reset and link bringup/teardown
|
2018-02-20 17:26:43 +08:00 |
|
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|
7e02d8245c
|
kasli: false paths
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
|
2018-02-19 13:05:11 +00:00 |
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0f4549655b
|
sayma: use Xilinx RX synchronizer
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
|
2018-02-19 17:49:53 +08:00 |
|
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52049cf36a
|
drtio: add Xilinx RX synchronizer
|
2018-02-19 17:49:43 +08:00 |
|
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3bc575bee7
|
drtio: add missing define for Sayma master
|
2018-02-19 17:11:21 +08:00 |
|
|
|
7376ab0ff8
|
drtio: fix Sayma after 83abdd28
|
2018-02-19 17:10:55 +08:00 |
|
Florent Kermarrec
|
f5831af535
|
drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down
|
2018-02-19 10:03:19 +01:00 |
|
Florent Kermarrec
|
89a158c0c9
|
drtio/transceiver/gtp_7series_init: remove dead code
|
2018-02-19 10:02:23 +01:00 |
|
Florent Kermarrec
|
782051f474
|
drtio/transceiver/gtp_7series_init: add no retiming on gtp resets
|
2018-02-19 09:59:50 +01:00 |
|
|
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01fa6c1c2e
|
reorganize examples
|
2018-02-19 15:46:08 +08:00 |
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4b4090518b
|
drtio: clean up remnants of removed debug functions
|
2018-02-19 15:14:32 +08:00 |
|
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c329c83676
|
kasli: fix disable_si5324_ibuf no_retiming
|
2018-02-19 12:19:05 +08:00 |
|
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a93decdef2
|
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
|
2018-02-19 00:48:37 +08:00 |
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94c20dfd4d
|
drtio: fix misleading GenericRXSynchronizer comment
|
2018-02-19 00:47:54 +08:00 |
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83abdd283a
|
drtio: signal stable clock input to transceiver
|
2018-02-18 22:29:30 +08:00 |
|
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c87636ed2b
|
si5324: fix cfb21ca
|
2018-02-18 11:38:20 +01:00 |
|
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|
caedcd5a15
|
ad9912: cleanup, document init()
|
2018-02-18 11:38:16 +01:00 |
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75c89422c9
|
ad991[02]: sysclk can be 1 GHz
|
2018-02-18 10:29:19 +00:00 |
|
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287d533437
|
Revert "sayma_amc: remove RTM bitstream upload core. Closes #908"
This reverts commit 2d4a1340ea.
|
2018-02-17 17:38:48 +08:00 |
|
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73985a9215
|
sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
|
2018-02-17 17:38:17 +08:00 |
|
|
|
039dee4c8e
|
si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
|
2018-02-17 13:54:50 +08:00 |
|
|
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cfb21ca126
|
si5324: fix usage of external CLKIN2 reference
|
2018-02-17 13:52:01 +08:00 |
|
|
|
fb8b36cd41
|
clean up ccc279b8
|
2018-02-17 12:10:46 +08:00 |
|
hartytp
|
ccc279b8da
|
rewrite HMC7043 init code without using ADI GUI outputs, working analog/digital delay
|
2018-02-17 12:07:11 +08:00 |
|
|
|
e41f49cc75
|
kasli: opticlock 125 MHz, mark external reference case broken
|
2018-02-16 17:23:15 +00:00 |
|
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7002bea0ab
|
kasli: clean up urukul example more
|
2018-02-15 14:21:17 +01:00 |
|
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4d42df2a7c
|
kasli: set up Si5324 in standalone operation
|
2018-02-15 20:32:58 +08:00 |
|
|
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c5ae81f452
|
satman: remove unused 62.5MHz Si5324 settings
|
2018-02-15 20:29:51 +08:00 |
|
|
|
d7387611c0
|
sayma: print RTM gateware version
|
2018-02-15 19:31:58 +08:00 |
|
whitequark
|
d572c0c34d
|
artiq_devtool: fix the hotswap action.
|
2018-02-14 23:10:27 +00:00 |
|
whitequark
|
fe50018037
|
firmware: make network tracing runtime switchable.
|
2018-02-14 23:03:20 +00:00 |
|
|
|
2adba3ed33
|
urukul: document ad9912, and cpld, fix api
|
2018-02-14 09:45:17 +01:00 |
|
|
|
ede98679fc
|
ad9910: add documentation
|
2018-02-14 09:05:03 +01:00 |
|
|
|
b6395a809b
|
kasli: remove old urukul test code
|
2018-02-13 22:16:57 +01:00 |
|
|
|
be693bc8a9
|
opticlock: examples
|
2018-02-13 22:13:40 +01:00 |
|
|
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a3d136d30d
|
opticlock: wire urukul and novogorny
|
2018-02-13 22:13:40 +01:00 |
|
|
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7f1bfddeda
|
ad9910: tweak spi timing for higher speed
|
2018-02-13 22:13:40 +01:00 |
|
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6a6695924f
|
urukul: proto 8
|
2018-02-13 22:13:40 +01:00 |
|
|
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bc6af03a61
|
urukul: (proto 7) drop att_le
|
2018-02-13 22:13:40 +01:00 |
|
|
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df177bfd5b
|
use new misoc identifier
|
2018-02-13 20:38:48 +08:00 |
|
|
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ab5f397fea
|
sed/fifos: use AsyncFIFOBuffered
(D)RTIO now passes timing at 150MHz on Kasli.
|
2018-02-13 20:02:51 +08:00 |
|
|
|
00f42f912b
|
rename 'RTM identifier' to 'RTM magic number'
Avoids confusion with the MiSoC identifier (containing the ARTIQ version).
|
2018-02-13 20:02:51 +08:00 |
|
|
|
96b948f57f
|
remote_csr: add sanity check of CSR CSV type column
|
2018-02-13 20:02:51 +08:00 |
|
|
|
e67a289e2b
|
examples: add SAWG sines (DAC synchronization test)
|
2018-02-13 20:02:51 +08:00 |
|
Florent Kermarrec
|
bfdda340fd
|
drtio/transceiver/gtp_7series: use parameters from xilinx wizard
|
2018-02-13 00:23:59 +01:00 |
|
Florent Kermarrec
|
180c28551d
|
drtio/gateware/transceiver/gtp_7series: add power down state before reset on rx (seems to make restart reliable)
|
2018-02-09 20:17:02 +01:00 |
|
|
|
2d4a1340ea
|
sayma_amc: remove RTM bitstream upload core. Closes #908
|
2018-02-07 12:27:35 +08:00 |
|
whitequark
|
61c64a76be
|
gateware: use a per-variant subfolder in --output-dir. (fixes #912)
This commit also adds support for --variant and --args
to artiq-devtool.
|
2018-02-06 08:19:01 +00:00 |
|
Florent Kermarrec
|
e80b481032
|
firmware/libboard_artiq/hmc830_7043.rs: add template for sys_ref phase configuration for dac1/dac2 and fpga
|
2018-02-05 13:40:17 +01:00 |
|
Florent Kermarrec
|
e50bebb63d
|
firmware/liboard_artiq/ad9154.rs: add checks for jesd subclass 1 (verify that we receive the sysref and that phase error is within the specified window error threshold).
|
2018-02-05 13:39:30 +01:00 |
|
|
|
9fca7b8faa
|
artiq_flash: also report sayma AMC SYSMONE1 data
requires hardware patch (https://github.com/m-labs/sinara/issues/495)
|
2018-01-30 15:17:11 +08:00 |
|
|
|
fb8c779b4f
|
artiq_flash: report XADC data
* bump openocd
* only kasli, kc705, sayma rtm so far
|
2018-01-30 14:56:50 +08:00 |
|
whitequark
|
807eb1155b
|
Update smoltcp.
Fixes #902.
|
2018-01-30 03:29:08 +00:00 |
|
whitequark
|
a669652854
|
artiq_flash: tell openocd to not listen on any network ports.
|
2018-01-30 03:12:06 +00:00 |
|
whitequark
|
0edc34a9e5
|
artiq_devtool: the proxy artiq_flash action doesn't exist anymore.
|
2018-01-28 15:19:17 +00:00 |
|
whitequark
|
885ab40946
|
conda: split RTM and AMC packages back.
This avoids multiplying the RTM compilation time by the number
of AMC packages.
|
2018-01-28 14:27:55 +00:00 |
|
whitequark
|
11a8b84355
|
Merge the build trees of sayma_amc and sayma_rtm targets.
This also makes them a single artiq_flash target, and a single
conda package.
|
2018-01-27 19:54:31 +00:00 |
|
whitequark
|
0b9c551962
|
artiq_flash: implement flash read functionality.
|
2018-01-27 19:54:31 +00:00 |
|
|
|
0aacdb0458
|
tools: add missing import
|
2018-01-28 02:12:46 +08:00 |
|
|
|
6f90a43df2
|
examples: reorganize for new hardware
|
2018-01-28 02:11:45 +08:00 |
|
|
|
67625fe912
|
test: check kernel overhead credibility
|
2018-01-28 01:02:03 +08:00 |
|
|
|
e8ed3475ea
|
test: add kernel overhead test (#407)
|
2018-01-28 01:00:59 +08:00 |
|
whitequark
|
eed2db3a98
|
artiq_flash: make the proxy action unnecessary.
|
2018-01-27 15:43:27 +00:00 |
|
whitequark
|
d58393a1e5
|
runtime: build with -Cpanic=unwind.
This is required for backtraces to function. I'm not sure how it
turned out that master had -Cpanic=abort.
|
2018-01-26 23:01:24 +00:00 |
|
whitequark
|
08101b631d
|
artiq_devtool: fix typo.
|
2018-01-26 13:55:31 +00:00 |
|
|
|
440e19b8f9
|
kasli: use SFP2 for DRTIO mastering
SFP1 PCB routing has some issues.
Also use SFP1 LED for DRTIO in both master and satellite.
|
2018-01-26 19:02:54 +08:00 |
|
|
|
0d2f89db53
|
si5324: chip does not ack RST_REG write
|
2018-01-25 11:06:19 +08:00 |
|
|
|
ca4d5ae73e
|
artiq_flash: add kasli drtio variants
|
2018-01-25 00:00:07 +08:00 |
|
|
|
77f90cf93b
|
test: relax RTIO counter test and print result
|
2018-01-24 10:07:22 +08:00 |
|
|
|
ed0fbd5662
|
test: add test for RTIO counter (#883)
|
2018-01-24 00:28:39 +08:00 |
|
|
|
e0e795f11c
|
sayma_amc: constrain pin, remove keep
|
2018-01-23 15:42:47 +00:00 |
|
|
|
b5c035bb52
|
sayma_rtm: constrain serwb clock input
|
2018-01-23 13:54:53 +00:00 |
|
|
|
aada38f508
|
kasli, kc705: remove vivado "keep", cleanup a constraint
|
2018-01-23 13:15:26 +00:00 |
|
|
|
85102e191e
|
sayma_rtm: derive clocks automatically
* also don't add false paths unless necessary
|
2018-01-23 11:00:55 +00:00 |
|
|
|
7d1b3f37c9
|
sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress
|
2018-01-23 10:56:42 +00:00 |
|
|
|
cb0016ceee
|
examples/sayma: fix ref_multiplier
SAWG is working, whoohoo!
|
2018-01-23 15:26:03 +08:00 |
|
|
|
cfffd9e13d
|
si5324: kasli support
|
2018-01-23 13:17:03 +08:00 |
|
|
|
649deccd9b
|
kasli: fix DRTIO satellite QPLL refclksel
|
2018-01-23 12:27:19 +08:00 |
|
|
|
4b4374f76a
|
sayma: register_jref for JESD204. Closes #904
|
2018-01-23 12:19:15 +08:00 |
|
|
|
763aefacff
|
kasli: fix typo
|
2018-01-23 12:10:54 +08:00 |
|
|
|
c7b148a704
|
kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1
|
2018-01-23 12:08:10 +08:00 |
|
|
|
d6157514c7
|
gtp_7series: flexible QPLL channel selection
|
2018-01-23 12:03:09 +08:00 |
|
|
|
9f87c34a94
|
kasli: fix QPLL instantiation
|
2018-01-23 10:39:31 +08:00 |
|
|
|
98a5607634
|
gtp_7series: set clock muxes correctly for second QPLL channel
|
2018-01-23 10:39:20 +08:00 |
|
|
|
25fee1a0bb
|
gtp_7series: use QPLL second channel
|
2018-01-23 10:15:49 +08:00 |
|
|
|
031d7ff020
|
kasli: keep using second QPLL channel for DRTIO satellite
|
2018-01-23 10:13:10 +08:00 |
|
|
|
626075cbc1
|
gtp_7series: simplify TX clocking
|
2018-01-23 09:49:23 +08:00 |
|
|
|
74b7baa8c5
|
urukul example: mmcx clock input
|
2018-01-22 20:30:08 +01:00 |
|
|
|
a86b28def2
|
urukul: example additions
* relax timings for faster spi xfers
* continuous readback test to explore spi speed limit
|
2018-01-22 20:29:30 +01:00 |
|
