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firmware/libboard_artiq/hmc830_7043.rs: add template for sys_ref phase configuration for dac1/dac2 and fpga

pull/922/head
Florent Kermarrec 2018-02-05 13:40:17 +01:00
parent e50bebb63d
commit e80b481032
1 changed files with 15 additions and 4 deletions
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19
artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -180,10 +180,21 @@ mod hmc7043 {
for &(addr, data) in HMC7043_WRITES.iter() {
write(addr, data);
}
/* sysref digital coarse delay configuration (18 steps, 1/2VCO cycle/step)*/
write(0x112, 0x0);
/* sysref analog fine delay configuration (24 steps, 25ps/step)*/
write(0x111, 0x0);
/* dac1 sysref digital coarse delay configuration (17 steps, 1/2VCO cycle/step)*/
write(0x0d6, 0);
/* dac1 sysref analog fine delay configuration (24 steps, 25ps/step)*/
write(0x0d5, 0);
/* dac2 sysref digital coarse delay configuration (17 steps, 1/2VCO cycle/step)*/
write(0x0ea, 0);
/* dac2 sysref analog fine delay configuration (24 steps, 25ps/step)*/
write(0x0e9, 0);
/* fpga sysref digital coarse delay configuration (17 steps, 1/2VCO cycle/step)*/
write(0x112, 0);
/* fpga sysref analog fine delay configuration (24 steps, 25ps/step)*/
write(0x111, 0);
Ok(())
}