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306 Commits

Author SHA1 Message Date
whitequark 11a8b84355 Merge the build trees of sayma_amc and sayma_rtm targets. 
This also makes them a single artiq_flash target, and a single
conda package.
 2018-01-27 19:54:31 +00:00
Sebastien Bourdeauducq 440e19b8f9 kasli: use SFP2 for DRTIO mastering 
SFP1 PCB routing has some issues.

Also use SFP1 LED for DRTIO in both master and satellite.
 2018-01-26 19:02:54 +08:00
Robert Jördens e0e795f11c sayma_amc: constrain pin, remove keep 2018-01-23 15:42:47 +00:00
Robert Jördens b5c035bb52 sayma_rtm: constrain serwb clock input 2018-01-23 13:54:53 +00:00
Robert Jördens aada38f508 kasli, kc705: remove vivado "keep", cleanup a constraint 2018-01-23 13:15:26 +00:00
Robert Jördens 85102e191e sayma_rtm: derive clocks automatically 
* also don't add false paths unless necessary
 2018-01-23 11:00:55 +00:00
Robert Jördens 7d1b3f37c9 sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress 2018-01-23 10:56:42 +00:00
Sebastien Bourdeauducq 649deccd9b kasli: fix DRTIO satellite QPLL refclksel 2018-01-23 12:27:19 +08:00
Sebastien Bourdeauducq 4b4374f76a sayma: register_jref for JESD204. Closes #904 2018-01-23 12:19:15 +08:00
Sebastien Bourdeauducq 763aefacff kasli: fix typo 2018-01-23 12:10:54 +08:00
Sebastien Bourdeauducq c7b148a704 kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1 2018-01-23 12:08:10 +08:00
Sebastien Bourdeauducq 9f87c34a94 kasli: fix QPLL instantiation 2018-01-23 10:39:31 +08:00
Sebastien Bourdeauducq 031d7ff020 kasli: keep using second QPLL channel for DRTIO satellite 2018-01-23 10:13:10 +08:00
Sebastien Bourdeauducq aa62e91487 kasli: add DRTIO targets (no firmware) 2018-01-23 01:27:40 +08:00
Sebastien Bourdeauducq 296ac35f5d sayma_amc: SFP TX disable is active-high 2018-01-23 00:32:09 +08:00
Sebastien Bourdeauducq 77192256ea kc705: style 2018-01-23 00:02:35 +08:00
Sebastien Bourdeauducq ab7c49d6d0 sayma_amc: raise error on invalid variant 2018-01-23 00:02:16 +08:00
Sebastien Bourdeauducq c1ac3b66b1 sayma_rtm: fix 8fe463d4a 2018-01-23 00:01:45 +08:00
Sebastien Bourdeauducq 53facfef13 sayma: build fixes 2018-01-22 18:33:22 +08:00
Sebastien Bourdeauducq 25f3feeda8 refactor targets 2018-01-22 18:25:10 +08:00
Sebastien Bourdeauducq 5198c224a2 sayma,kasli: use new pin names 2018-01-22 11:51:07 +08:00
Florent Kermarrec 8fe463d4a0 sayma_rtm: add UART loopback to easily know if rtm fpga is alive 2018-01-20 06:04:34 +01:00
Florent Kermarrec 74ce7319d3 sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?) 2018-01-20 06:04:18 +01:00
Sebastien Bourdeauducq cdbf95d46a kasli: fix permissions 2018-01-19 18:31:20 +08:00
Robert Jördens 8ec33ae7bd kasli: feed EEM clock fan-out from SI5324 2018-01-17 17:27:59 +01:00
Robert Jördens ed3e3b2791 sayma_amc: clarify --with-sawg help 2018-01-17 12:10:30 +01:00
Florent Kermarrec f54b27b79c sayma_amc: prepare for jesd subclass 1 2018-01-17 11:49:36 +01:00
Robert Jördens 7405006668 sayma: rtio clock is jesd fabric clock 2018-01-16 18:19:04 +01:00
whitequark 444b901dbe sayma: add RTM configuration port. 2018-01-16 07:28:00 +00:00
whitequark 6891141fa6 artiq_flash: add sayma support. 2018-01-15 11:43:29 +00:00
Robert Jördens ac3c3871d0 kasli: s/extensions/variant/g 2018-01-12 12:29:42 +01:00
Sebastien Bourdeauducq 7c82fcf41a targets: avoid passing cpu_type around unnecessarily 2018-01-11 11:21:55 +08:00
Sebastien Bourdeauducq 6d58c4390b Merge branch 'sed-merge' 2018-01-10 13:14:39 +08:00
Sebastien Bourdeauducq 04b2fd3e13 sayma: fix AD9154NoSAWG ramp clock domain 2018-01-10 12:11:33 +08:00
Sebastien Bourdeauducq dc593ec0f0 Merge branch 'rtio-sed' into sed-merge 2018-01-10 12:04:54 +08:00
Robert Jördens 8813aee6b1 targets: add kasli [wip, untested] 2018-01-04 16:12:12 +01:00
Florent Kermarrec 1e972034e8 gateware/targets: enable serwb scrambling on sayma amc & rtm 2018-01-03 17:34:46 +01:00
Robert Jördens c2be820e9a kc705_dds: make ext_clkout 100 MHz 2018-01-02 19:58:47 +01:00
Robert Jördens 43686f324b kc705_dds: fix HPC voltages 
* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V

* the direction control register on HPC (FMC-DIO to VHDCI)
  was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
  they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
  and hope for the best.
 2018-01-02 13:41:07 +01:00
Robert Jördens 94b84ebe7c kc705_dds: add urukul spi/ttl channels 2018-01-02 13:20:48 +01:00
Robert Jördens 53969d3686 kc705_dds: add urukul on vhdci extension definition 2018-01-02 13:20:47 +01:00
Robert Jördens 745e695b09 sayma: output a ramp in the absence of SAWG channels 2017-12-31 12:18:53 +01:00
whitequark a371b25525 bootloader: allow using without Ethernet. 2017-12-31 09:21:28 +00:00
Robert Jördens 379d29561b sayma: plausibility assertion on sawg data stream 2017-12-29 19:15:40 +01:00
Sebastien Bourdeauducq 6801921fc0 drtio: instrument GTH transceiver 2017-12-28 15:03:14 +08:00
Sebastien Bourdeauducq 70b7f28ad3 drtio: drive SFP TX disable pins 2017-12-23 22:58:51 +08:00
Sebastien Bourdeauducq 1af21c0b29 drtio: integrate GTH transceiver for Sayma 2017-12-23 01:19:59 +08:00
Sebastien Bourdeauducq ebdbaaad32 drtio: remove KC705/GTX support 2017-12-22 17:51:42 +08:00
Sebastien Bourdeauducq 0681d472c7 conda: fix sayma_rtm_csr.csv location for Sayma AMC 2017-12-22 17:14:10 +08:00
Sebastien Bourdeauducq 44959144d8 conda: add Sayma AMC standalone board package 2017-12-22 16:44:04 +08:00