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14c7b4890c
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rustc: enable lld
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2019-06-05 23:05:15 +08:00 |
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d02da47167
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minerva: bump
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2019-05-25 12:23:17 +08:00 |
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2f3c1824a6
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nmigen: bump
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2019-05-15 18:55:32 +08:00 |
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ec09c09cf3
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rust-riscv32i-crates: use external compiler_builtins
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2019-05-14 20:35:40 +08:00 |
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a0690fe0e2
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rust-riscv32i-crates: disable compiler_builtins
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2019-05-14 19:58:13 +08:00 |
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9e93a9cf39
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rustc: make llvm override compatible with nixos-unstable
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2019-05-14 19:17:16 +08:00 |
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9f4538555e
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fix previous commit
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2019-05-14 19:16:52 +08:00 |
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e9b005d50a
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mark riscv rustc
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2019-05-14 19:05:30 +08:00 |
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677ddefff2
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mark riscv llvm
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2019-05-14 14:07:36 +08:00 |
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351d5360f0
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llvm -> llvm_7 for nixos-unstable rustc
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2019-05-14 10:41:10 +08:00 |
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f7e7b894b7
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simplesoc_ecp5: disable minerva muldiv
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2019-05-13 00:46:52 +08:00 |
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52f663eda6
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minerva: bump
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2019-05-13 00:46:43 +08:00 |
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05822f0a36
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simplesoc_ecp5: remove nmigen/#30 workaround
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2019-05-12 15:01:45 +08:00 |
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c77c296e72
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nmigen: bump
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2019-05-12 14:58:08 +08:00 |
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e74b5dfe00
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ecp5: use speed grade 8 (versa)
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2019-05-06 22:44:58 +08:00 |
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7ffce5882e
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add simplesoc_ecp5 to continuous build
|
2019-05-02 12:54:57 +08:00 |
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5bc9189709
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add simplesoc_ecp5 (WIP)
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2019-05-02 12:53:28 +08:00 |
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70638e6d87
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add wishbone components
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2019-05-02 12:53:08 +08:00 |
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88db84cfd7
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uart: style
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2019-05-02 12:52:29 +08:00 |
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d765dfb7b9
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add __all__
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2019-05-01 17:05:19 +08:00 |
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d84b172245
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helloworld_ecp5: add delays between messages
Otherwise the FTDI UART goes out of sync and corrupts data.
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2019-04-30 15:52:41 +08:00 |
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1cf460b56f
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helloworld_ecp5: fix serial_tx location
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2019-04-30 13:36:09 +08:00 |
|
Charles Papon
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7d227ba4c5
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Update to SpinalHDL 1.3.3 VexRiscv 1.1
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2019-04-28 20:49:45 +08:00 |
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83bbf62f04
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nmigen: bump
|
2019-04-27 15:00:07 +08:00 |
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73ef6dcfe8
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yosys: update version number
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2019-04-27 14:59:16 +08:00 |
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4052e4ff93
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yosys: bump
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2019-04-27 14:45:05 +08:00 |
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fe7ee7b58d
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helloworld_ecp5: fix LPF
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2019-04-27 14:39:34 +08:00 |
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263b04245e
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add continuous build for helloworld examples
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2019-04-26 18:27:06 +08:00 |
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5436920008
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add ECP5 helloworld
|
2019-04-26 18:22:23 +08:00 |
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3b2f6a222e
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cleanup
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2019-04-26 17:43:31 +08:00 |
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40eced0136
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vivado.nix: revert accidentally committed part
|
2019-04-26 17:01:26 +08:00 |
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86e0299200
|
helloworld_kintex7: fix
|
2019-04-26 16:59:19 +08:00 |
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a19f0784d0
|
use Elaboratable
|
2019-04-26 16:57:59 +08:00 |
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347e858ece
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helloworld -> helloworld_kintex7
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2019-04-26 16:56:47 +08:00 |
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05974f272d
|
bump minerva
|
2019-04-22 14:40:17 +08:00 |
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dd64f92754
|
bump nmigen
|
2019-04-22 14:40:04 +08:00 |
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2bd819fcbe
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roundrobin: use nmigen zero-width signals
|
2019-04-18 11:58:51 +08:00 |
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e14031fba6
|
add round-robin arbiter
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2019-04-17 20:18:41 +08:00 |
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034ecc4d99
|
nmigen: run tests in verbose mode
|
2019-04-17 16:08:37 +08:00 |
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4dd024942e
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nmigen: bump
|
2019-04-17 16:08:18 +08:00 |
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e3f47815e5
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rust: add riscv32i
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2019-04-09 00:48:19 +08:00 |
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25fe837684
|
use upstream rust/llvm
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2019-04-09 00:09:58 +08:00 |
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c3992220e5
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rustc: fix crates compilation
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2019-04-07 23:16:00 +08:00 |
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da982a60cc
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rustc: add libxml2 dep
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2019-04-07 00:45:02 +08:00 |
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0ef16ba90c
|
llvm: use more up-to-date upstream, build for riscv
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2019-04-06 21:25:34 +08:00 |
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52dbb6275f
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rust: fix riscv target name
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2019-04-06 20:06:09 +08:00 |
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96b7248514
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rustc: use more up-to-date upstream, build for riscv
|
2019-04-06 19:16:34 +08:00 |
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b913a92a82
|
add rustc (WIP)
|
2019-04-06 18:23:31 +08:00 |
|
|
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298514fe0a
|
move fetch-llvm-clang.nix into llvm-hx.nix
|
2019-04-06 15:20:49 +08:00 |
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|
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1bf9b5eb2b
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add VexRiscv
|
2019-04-05 18:58:11 +08:00 |
|
