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@ -45,22 +45,6 @@ class Top(Elaboratable): |
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(lambda a: a[20], uart.bus) |
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], register=True) |
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# work around https://github.com/m-labs/nmigen/issues/30 |
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m.d.comb += [ |
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cpu.external_interrupt.eq(0), |
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cpu.timer_interrupt.eq(0), |
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cpu.fetch.ibus.dat_w.eq(0), |
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cpu.fetch.ibus.sel.eq(0b1111), |
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cpu.fetch.ibus.we.eq(0), |
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cpu.fetch.ibus.cti.eq(0), |
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cpu.fetch.ibus.bte.eq(0), |
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cpu.loadstore.dbus.cti.eq(0), |
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cpu.loadstore.dbus.bte.eq(0), |
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ram.bus.err.eq(0), |
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uart.bus.err.eq(0), |
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uart.bus.dat_r.eq(0) |
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] |
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return m |
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