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simplesoc_ecp5: remove nmigen/#30 workaround

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This commit is contained in:
Sebastien Bourdeauducq 2019-05-12 15:01:45 +08:00
parent c77c296e72
commit 05822f0a36
1 changed files with 0 additions and 16 deletions
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examples/simplesoc_ecp5.py
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@ -45,22 +45,6 @@ class Top(Elaboratable):
(lambda a: a[20], uart.bus)
], register=True)
# work around https://github.com/m-labs/nmigen/issues/30
m.d.comb += [
cpu.external_interrupt.eq(0),
cpu.timer_interrupt.eq(0),
cpu.fetch.ibus.dat_w.eq(0),
cpu.fetch.ibus.sel.eq(0b1111),
cpu.fetch.ibus.we.eq(0),
cpu.fetch.ibus.cti.eq(0),
cpu.fetch.ibus.bte.eq(0),
cpu.loadstore.dbus.cti.eq(0),
cpu.loadstore.dbus.bte.eq(0),
ram.bus.err.eq(0),
uart.bus.err.eq(0),
uart.bus.dat_r.eq(0)
]
return m