add VexRiscv
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parent
584dba9ed0
commit
1bf9b5eb2b
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@ -0,0 +1,28 @@
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{ runCommand, fetchFromGitHub, makeWrapper, scala-spinalhdl, name, scalaToRun }:
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let
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vexriscv-src = fetchFromGitHub {
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rev = "d63c6818df8c7229ee9c2ffa83181748b930e1d9";
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owner = "SpinalHDL";
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repo = "VexRiscv";
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sha256 = "1q707icib7q7x9njm4f73g36jjs9q1cvfpv10w6a4jhswg63zyga";
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};
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vexriscv-compiled = runCommand "vexriscv-compiled" {}
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''
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mkdir $out
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${scala-spinalhdl}/bin/scalac-spinalhdl -d $out/VexRiscv.jar `find ${vexriscv-src}/src/main/scala -type f`
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'';
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scala-vexriscv = runCommand "scala-vexriscv" { nativeBuildInputs = [ makeWrapper ]; }
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''
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mkdir -p $out/bin
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makeWrapper ${scala-spinalhdl}/bin/scala-spinalhdl $out/bin/scala-vexriscv --prefix CLASSPATH : ${vexriscv-compiled}/VexRiscv.jar
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'';
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in
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runCommand name {}
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''
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mkdir $out
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cd $out
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${scala-vexriscv}/bin/scala-vexriscv ${scalaToRun}
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mkdir -p $out/nix-support
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echo file verilog $out/VexRiscv.v >> $out/nix-support/hydra-build-products
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''
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@ -7,6 +7,11 @@ rec {
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jtagtap = pkgs.callPackage ./cores/jtagtap.nix { inherit nmigen; };
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minerva = pkgs.callPackage ./cores/minerva.nix { inherit nmigen; inherit jtagtap; };
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vexriscv-small = pkgs.callPackage ./cores/vexriscv.nix {
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inherit scala-spinalhdl;
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name = "vexriscv-small";
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scalaToRun = "vexriscv.demo.GenSmallAndProductive";
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};
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heavycomps = pkgs.callPackage ./heavycomps.nix { inherit nmigen; };
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@ -33,4 +33,5 @@ in
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''
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mkdir -p $out/bin
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makeWrapper ${scala_2_11}/bin/scala $out/bin/scala-spinalhdl --prefix CLASSPATH : ${fmtJars}
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makeWrapper ${scala_2_11}/bin/scalac $out/bin/scalac-spinalhdl --prefix CLASSPATH : ${fmtJars}
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''
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