Next-generation FPGA SoC toolkit

Sebastien Bourdeauducq d84b172245 helloworld_ecp5: add delays between messages ... Otherwise the FTDI UART goes out of sync and corrupts data.		2019-04-30 15:52:41 +08:00
compilers	rust: add riscv32i	2019-04-09 00:48:19 +08:00
cores	Update to SpinalHDL 1.3.3 VexRiscv 1.1	2019-04-28 20:49:45 +08:00
eda	Update to SpinalHDL 1.3.3 VexRiscv 1.1	2019-04-28 20:49:45 +08:00
examples	helloworld_ecp5: add delays between messages	2019-04-30 15:52:41 +08:00
heavycomps	use Elaboratable	2019-04-26 16:57:59 +08:00
.gitignore	add nix-build results to .gitignore	2019-03-25 23:36:52 +08:00
default.nix	add ECP5 helloworld	2019-04-26 18:22:23 +08:00
derivations.nix	rust: add riscv32i	2019-04-09 00:48:19 +08:00
heavycomps.nix	add component library with UART	2019-03-19 16:52:02 +08:00
release.nix	add continuous build for helloworld examples	2019-04-26 18:27:06 +08:00